NAME=ATmega640/1280/1281/2560/2561
FILE=ihex://bins/avr/nRF24L01_ATmega640.hex
CMDS=<<EOF
ia
flt
pd 60 @ 0
EOF
EXPECT=<<EOF
[Info]
arch     avr
cpu      ATmega2561
features N/A
baddr    ----------
binsz    0x00001c52
bintype  N/A
bits     8
class    N/A
compiler N/A
dbg_file N/A
endian   LE
hdr.csum N/A
guid     N/A
intrp    N/A
laddr    0x00000000
lang     N/A
machine  ATmega640/1280/1281/2560/2561
maxopsz  4
minopsz  2
os       avr usermode
cc       N/A
pcalign  2
rpath    N/A
subsys   
stripped false
havecode true
va       false
static   true
linenum  false
lsyms    false
canary   false
pie      false
relrocs  false
nx       false

[Imports]
nth vaddr bind type lib name 
-----------------------------

[Entries]
     vaddr      paddr     hvaddr      haddr type    
----------------------------------------------------
0x00000000 0x00000000 ---------- ---------- program
0x000000e4 0x000000e4 0x000000e4 0x000000e4 init

[Exports]
nth paddr vaddr bind type size lib name 
----------------------------------------

[Classes]
address min max name super 
---------------------------

[Symbols]
nth      paddr      vaddr bind type size lib name               
----------------------------------------------------------------
  0 0x0000011e 0x0000011e NONE NONE    0     __bad_interrupt
  0 0x00000000 0x00000000 NONE NONE    0     vector.RESET
  0 0x000000e4 0x000000e4 NONE NONE    0     handler.RESET
  0 0x00000004 0x00000004 NONE NONE    0     vector.INT0
  0 0x00000008 0x00000008 NONE NONE    0     vector.INT1
  0 0x00001288 0x00001288 NONE NONE    0     handler.INT1
  0 0x0000000c 0x0000000c NONE NONE    0     vector.INT2
  0 0x00000010 0x00000010 NONE NONE    0     vector.INT3
  0 0x000014fa 0x000014fa NONE NONE    0     handler.INT3
  0 0x00000014 0x00000014 NONE NONE    0     vector.INT4
  0 0x00000018 0x00000018 NONE NONE    0     vector.INT5
  0 0x00001306 0x00001306 NONE NONE    0     handler.INT5
  0 0x0000001c 0x0000001c NONE NONE    0     vector.INT6
  0 0x00000020 0x00000020 NONE NONE    0     vector.INT7
  0 0x00000024 0x00000024 NONE NONE    0     vector.PCINT0
  0 0x00000028 0x00000028 NONE NONE    0     vector.PCINT1
  0 0x0000002c 0x0000002c NONE NONE    0     vector.PCINT2
  0 0x00000030 0x00000030 NONE NONE    0     vector.WDT
  0 0x00000034 0x00000034 NONE NONE    0     vector.TIM2_COMPA
  0 0x00000038 0x00000038 NONE NONE    0     vector.TIM2_COMPB
  0 0x0000003c 0x0000003c NONE NONE    0     vector.TIM2_OVF
  0 0x00000040 0x00000040 NONE NONE    0     vector.TIM1_CAPT
  0 0x00000044 0x00000044 NONE NONE    0     vector.TIM1_COMPA
  0 0x00000048 0x00000048 NONE NONE    0     vector.TIM1_COMPB
  0 0x0000004c 0x0000004c NONE NONE    0     vector.TIM1_COMPC
  0 0x00000050 0x00000050 NONE NONE    0     vector.TIM1_OVF
  0 0x00000054 0x00000054 NONE NONE    0     vector.TIM0_COMPA
  0 0x00000058 0x00000058 NONE NONE    0     vector.TIM0_COMPB
  0 0x0000005c 0x0000005c NONE NONE    0     vector.TIM0_OVF
  0 0x00000060 0x00000060 NONE NONE    0     vector.SPI_STC
  0 0x00000064 0x00000064 NONE NONE    0     vector.USART0_RXC
  0 0x00000068 0x00000068 NONE NONE    0     vector.USART0_UDRE
  0 0x0000006c 0x0000006c NONE NONE    0     vector.USART0_TXC
  0 0x00000070 0x00000070 NONE NONE    0     vector.ANA_COMP
  0 0x00000074 0x00000074 NONE NONE    0     vector.ADC
  0 0x00000078 0x00000078 NONE NONE    0     vector.EE_RDY
  0 0x0000007c 0x0000007c NONE NONE    0     vector.TIM3_CAPT
  0 0x00000080 0x00000080 NONE NONE    0     vector.TIM3_COMPA
  0 0x000011ca 0x000011ca NONE NONE    0     handler.TIM3_COMPA
  0 0x00000084 0x00000084 NONE NONE    0     vector.TIM3_COMPB
  0 0x00000088 0x00000088 NONE NONE    0     vector.TIM3_COMPC
  0 0x0000008c 0x0000008c NONE NONE    0     vector.TIM3_OVF
  0 0x00000090 0x00000090 NONE NONE    0     vector.USART1_RXC
  0 0x00000094 0x00000094 NONE NONE    0     vector.USART1_UDRE
  0 0x00000098 0x00000098 NONE NONE    0     vector.USART1_TXC
  0 0x0000009c 0x0000009c NONE NONE    0     vector.TWI
  0 0x000000a0 0x000000a0 NONE NONE    0     vector.SPM_RDY
  0 0x000000a4 0x000000a4 NONE NONE    0     vector.TIM4_CAPT
  0 0x000000a8 0x000000a8 NONE NONE    0     vector.TIM4_COMPA
  0 0x000000ac 0x000000ac NONE NONE    0     vector.TIM4_COMPB
  0 0x000000b0 0x000000b0 NONE NONE    0     vector.TIM4_COMPC
  0 0x000000b4 0x000000b4 NONE NONE    0     vector.TIM4_OVF
  0 0x000000b8 0x000000b8 NONE NONE    0     vector.TIM5_CAPT
  0 0x000000bc 0x000000bc NONE NONE    0     vector.TIM5_COMPA
  0 0x000000c0 0x000000c0 NONE NONE    0     vector.TIM5_COMPB
  0 0x000000c4 0x000000c4 NONE NONE    0     vector.TIM5_COMPC
  0 0x000000c8 0x000000c8 NONE NONE    0     vector.TIM5_OVF
  0 0x000000cc 0x000000cc NONE NONE    0     vector.USART2_RXC
  0 0x000000d0 0x000000d0 NONE NONE    0     vector.USART2_UDRE
  0 0x000000d4 0x000000d4 NONE NONE    0     vector.USART2_TXC
  0 0x000000d8 0x000000d8 NONE NONE    0     vector.USART3_RXC
  0 0x000000dc 0x000000dc NONE NONE    0     vector.USART3_UDRE
  0 0x000000e0 0x000000e0 NONE NONE    0     vector.USART3_TXC

[Sections]
paddr size vaddr vsize align perm name type flags 
--------------------------------------------------

[Memory]
name size address flags mirror 
-------------------------------

[Strings]
paddr vaddr len size section type string 
-----------------------------------------

      addr size space   name                   realname           
------------------------------------------------------------------
0x00000000    1 symbols entry0                 entry0
0x00000000    0 symbols sym.vector.RESET       vector.RESET
0x00000004    0 symbols sym.vector.INT0        vector.INT0
0x00000008    0 symbols sym.vector.INT1        vector.INT1
0x0000000c    0 symbols sym.vector.INT2        vector.INT2
0x00000010    0 symbols sym.vector.INT3        vector.INT3
0x00000014    0 symbols sym.vector.INT4        vector.INT4
0x00000018    0 symbols sym.vector.INT5        vector.INT5
0x0000001c    0 symbols sym.vector.INT6        vector.INT6
0x00000020    0 symbols sym.vector.INT7        vector.INT7
0x00000024    0 symbols sym.vector.PCINT0      vector.PCINT0
0x00000028    0 symbols sym.vector.PCINT1      vector.PCINT1
0x0000002c    0 symbols sym.vector.PCINT2      vector.PCINT2
0x00000030    0 symbols sym.vector.WDT         vector.WDT
0x00000034    0 symbols sym.vector.TIM2_COMPA  vector.TIM2_COMPA
0x00000038    0 symbols sym.vector.TIM2_COMPB  vector.TIM2_COMPB
0x0000003c    0 symbols sym.vector.TIM2_OVF    vector.TIM2_OVF
0x00000040    0 symbols sym.vector.TIM1_CAPT   vector.TIM1_CAPT
0x00000044    0 symbols sym.vector.TIM1_COMPA  vector.TIM1_COMPA
0x00000048    0 symbols sym.vector.TIM1_COMPB  vector.TIM1_COMPB
0x0000004c    0 symbols sym.vector.TIM1_COMPC  vector.TIM1_COMPC
0x00000050    0 symbols sym.vector.TIM1_OVF    vector.TIM1_OVF
0x00000054    0 symbols sym.vector.TIM0_COMPA  vector.TIM0_COMPA
0x00000058    0 symbols sym.vector.TIM0_COMPB  vector.TIM0_COMPB
0x0000005c    0 symbols sym.vector.TIM0_OVF    vector.TIM0_OVF
0x00000060    0 symbols sym.vector.SPI_STC     vector.SPI_STC
0x00000064    0 symbols sym.vector.USART0_RXC  vector.USART0_RXC
0x00000068    0 symbols sym.vector.USART0_UDRE vector.USART0_UDRE
0x0000006c    0 symbols sym.vector.USART0_TXC  vector.USART0_TXC
0x00000070    0 symbols sym.vector.ANA_COMP    vector.ANA_COMP
0x00000074    0 symbols sym.vector.ADC         vector.ADC
0x00000078    0 symbols sym.vector.EE_RDY      vector.EE_RDY
0x0000007c    0 symbols sym.vector.TIM3_CAPT   vector.TIM3_CAPT
0x00000080    0 symbols sym.vector.TIM3_COMPA  vector.TIM3_COMPA
0x00000084    0 symbols sym.vector.TIM3_COMPB  vector.TIM3_COMPB
0x00000088    0 symbols sym.vector.TIM3_COMPC  vector.TIM3_COMPC
0x0000008c    0 symbols sym.vector.TIM3_OVF    vector.TIM3_OVF
0x00000090    0 symbols sym.vector.USART1_RXC  vector.USART1_RXC
0x00000094    0 symbols sym.vector.USART1_UDRE vector.USART1_UDRE
0x00000098    0 symbols sym.vector.USART1_TXC  vector.USART1_TXC
0x0000009c    0 symbols sym.vector.TWI         vector.TWI
0x000000a0    0 symbols sym.vector.SPM_RDY     vector.SPM_RDY
0x000000a4    0 symbols sym.vector.TIM4_CAPT   vector.TIM4_CAPT
0x000000a8    0 symbols sym.vector.TIM4_COMPA  vector.TIM4_COMPA
0x000000ac    0 symbols sym.vector.TIM4_COMPB  vector.TIM4_COMPB
0x000000b0    0 symbols sym.vector.TIM4_COMPC  vector.TIM4_COMPC
0x000000b4    0 symbols sym.vector.TIM4_OVF    vector.TIM4_OVF
0x000000b8    0 symbols sym.vector.TIM5_CAPT   vector.TIM5_CAPT
0x000000bc    0 symbols sym.vector.TIM5_COMPA  vector.TIM5_COMPA
0x000000c0    0 symbols sym.vector.TIM5_COMPB  vector.TIM5_COMPB
0x000000c4    0 symbols sym.vector.TIM5_COMPC  vector.TIM5_COMPC
0x000000c8    0 symbols sym.vector.TIM5_OVF    vector.TIM5_OVF
0x000000cc    0 symbols sym.vector.USART2_RXC  vector.USART2_RXC
0x000000d0    0 symbols sym.vector.USART2_UDRE vector.USART2_UDRE
0x000000d4    0 symbols sym.vector.USART2_TXC  vector.USART2_TXC
0x000000d8    0 symbols sym.vector.USART3_RXC  vector.USART3_RXC
0x000000dc    0 symbols sym.vector.USART3_UDRE vector.USART3_UDRE
0x000000e0    0 symbols sym.vector.USART3_TXC  vector.USART3_TXC
0x000000e4  256 symbols main                   main
0x000000e4    1 symbols entry.init0            entry.init0
0x000000e4    0 symbols sym.handler.RESET      handler.RESET
0x0000011e    0 symbols sym.__bad_interrupt    __bad_interrupt
0x000011ca    0 symbols sym.handler.TIM3_COMPA handler.TIM3_COMPA
0x00001288    0 symbols sym.handler.INT1       handler.INT1
0x00001306    0 symbols sym.handler.INT5       handler.INT5
0x000014fa    0 symbols sym.handler.INT3       handler.INT3
            ;-- entry0:
            ;-- vector.RESET:
        ,=< 0x00000000      jmp   0xe4
        |   ;-- vector.INT0:
       ,==< 0x00000004      jmp   sym.__bad_interrupt
       ||   ;-- vector.INT1:
      ,===< 0x00000008      jmp   sym.handler.INT1
      |||   ;-- vector.INT2:
     ,====< 0x0000000c      jmp   sym.__bad_interrupt
     ||||   ;-- vector.INT3:
    ,=====< 0x00000010      jmp   sym.handler.INT3
    |||||   ;-- vector.INT4:
   ,======< 0x00000014      jmp   sym.__bad_interrupt
   ||||||   ;-- vector.INT5:
  ,=======< 0x00000018      jmp   sym.handler.INT5
  |||||||   ;-- vector.INT6:
  ========< 0x0000001c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.INT7:
  ========< 0x00000020      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.PCINT0:
  ========< 0x00000024      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.PCINT1:
  ========< 0x00000028      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.PCINT2:
  ========< 0x0000002c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.WDT:
  ========< 0x00000030      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM2_COMPA:
  ========< 0x00000034      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM2_COMPB:
  ========< 0x00000038      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM2_OVF:
  ========< 0x0000003c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_CAPT:
  ========< 0x00000040      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_COMPA:
  ========< 0x00000044      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_COMPB:
  ========< 0x00000048      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_COMPC:
  ========< 0x0000004c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_OVF:
  ========< 0x00000050      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM0_COMPA:
  ========< 0x00000054      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM0_COMPB:
  ========< 0x00000058      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM0_OVF:
  ========< 0x0000005c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.SPI_STC:
  ========< 0x00000060      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART0_RXC:
  ========< 0x00000064      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART0_UDRE:
  ========< 0x00000068      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART0_TXC:
  ========< 0x0000006c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.ANA_COMP:
  ========< 0x00000070      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.ADC:
  ========< 0x00000074      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.EE_RDY:
  ========< 0x00000078      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM3_CAPT:
  ========< 0x0000007c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM3_COMPA:
  ========< 0x00000080      jmp   sym.handler.TIM3_COMPA
  |||||||   ;-- vector.TIM3_COMPB:
  ========< 0x00000084      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM3_COMPC:
  ========< 0x00000088      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM3_OVF:
  ========< 0x0000008c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART1_RXC:
  ========< 0x00000090      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART1_UDRE:
  ========< 0x00000094      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART1_TXC:
  ========< 0x00000098      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TWI:
  ========< 0x0000009c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.SPM_RDY:
  ========< 0x000000a0      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM4_CAPT:
  ========< 0x000000a4      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM4_COMPA:
  ========< 0x000000a8      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM4_COMPB:
  ========< 0x000000ac      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM4_COMPC:
  ========< 0x000000b0      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM4_OVF:
  ========< 0x000000b4      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM5_CAPT:
  ========< 0x000000b8      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM5_COMPA:
  ========< 0x000000bc      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM5_COMPB:
  ========< 0x000000c0      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM5_COMPC:
  ========< 0x000000c4      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM5_OVF:
  ========< 0x000000c8      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART2_RXC:
  ========< 0x000000cc      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART2_UDRE:
  ========< 0x000000d0      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART2_TXC:
  ========< 0x000000d4      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART3_RXC:
  ========< 0x000000d8      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART3_UDRE:
  ========< 0x000000dc      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART3_TXC:
  ========< 0x000000e0      jmp   sym.__bad_interrupt
  |||||||   ;-- main:
  |||||||   ;-- entry.init0:
  |||||||   ;-- handler.RESET:
  ||||||`-> 0x000000e4      clr   r1
  ||||||    0x000000e6      out   SREG, r1
  ||||||    0x000000e8      ser   r28
EOF
RUN

NAME=ATmega2560 with rcall 0xffff
FILE=ihex://bins/avr/atmega2560.hex
CMDS=<<EOF
ia
flt
pd 120 @ 0
EOF
EXPECT=<<EOF
[Info]
arch     avr
cpu      ATmega2561
features N/A
baddr    ----------
binsz    0x0003e07e
bintype  N/A
bits     8
class    N/A
compiler N/A
dbg_file N/A
endian   LE
hdr.csum N/A
guid     N/A
intrp    N/A
laddr    0x00000000
lang     N/A
machine  ATmega640/1280/1281/2560/2561
maxopsz  4
minopsz  2
os       avr usermode
cc       N/A
pcalign  2
rpath    N/A
subsys   
stripped false
havecode true
va       false
static   true
linenum  false
lsyms    false
canary   false
pie      false
relrocs  false
nx       false

[Imports]
nth vaddr bind type lib name 
-----------------------------

[Entries]
     vaddr      paddr     hvaddr      haddr type    
----------------------------------------------------
0x00000000 0x00000000 ---------- ---------- program
0x00001cf0 0x00001cf0 0x00001cf0 0x00001cf0 init

[Exports]
nth paddr vaddr bind type size lib name 
----------------------------------------

[Classes]
address min max name super 
---------------------------

[Symbols]
nth      paddr      vaddr bind type size lib name               
----------------------------------------------------------------
  0 0x00000000 0x00000000 NONE NONE    0     vector.RESET
  0 0x00001cf0 0x00001cf0 NONE NONE    0     handler.RESET
  0 0x00000004 0x00000004 NONE NONE    0     vector.INT0
  0 0x00000248 0x00000248 NONE NONE    0     handler.INT0
  0 0x00000008 0x00000008 NONE NONE    0     vector.INT1
  0 0x0000000c 0x0000000c NONE NONE    0     vector.INT2
  0 0x00000010 0x00000010 NONE NONE    0     vector.INT3
  0 0x00000014 0x00000014 NONE NONE    0     vector.INT4
  0 0x00000018 0x00000018 NONE NONE    0     vector.INT5
  0 0x0000001c 0x0000001c NONE NONE    0     vector.INT6
  0 0x00000020 0x00000020 NONE NONE    0     vector.INT7
  0 0x00000024 0x00000024 NONE NONE    0     vector.PCINT0
  0 0x00000028 0x00000028 NONE NONE    0     vector.PCINT1
  0 0x0000002c 0x0000002c NONE NONE    0     vector.PCINT2
  0 0x00000030 0x00000030 NONE NONE    0     vector.WDT
  0 0x00000034 0x00000034 NONE NONE    0     vector.TIM2_COMPA
  0 0x00000038 0x00000038 NONE NONE    0     vector.TIM2_COMPB
  0 0x0000003c 0x0000003c NONE NONE    0     vector.TIM2_OVF
  0 0x00000040 0x00000040 NONE NONE    0     vector.TIM1_CAPT
  0 0x00000044 0x00000044 NONE NONE    0     vector.TIM1_COMPA
  0 0x00000048 0x00000048 NONE NONE    0     vector.TIM1_COMPB
  0 0x0000004c 0x0000004c NONE NONE    0     vector.TIM1_COMPC
  0 0x00000050 0x00000050 NONE NONE    0     vector.TIM1_OVF
  0 0x00000054 0x00000054 NONE NONE    0     vector.TIM0_COMPA
  0 0x00000058 0x00000058 NONE NONE    0     vector.TIM0_COMPB
  0 0x0000005c 0x0000005c NONE NONE    0     vector.TIM0_OVF
  0 0x00000060 0x00000060 NONE NONE    0     vector.SPI_STC
  0 0x00000064 0x00000064 NONE NONE    0     vector.USART0_RXC
  0 0x00000068 0x00000068 NONE NONE    0     vector.USART0_UDRE
  0 0x0000006c 0x0000006c NONE NONE    0     vector.USART0_TXC
  0 0x00000070 0x00000070 NONE NONE    0     vector.ANA_COMP
  0 0x00000074 0x00000074 NONE NONE    0     vector.ADC
  0 0x00000078 0x00000078 NONE NONE    0     vector.EE_RDY
  0 0x0000007c 0x0000007c NONE NONE    0     vector.TIM3_CAPT
  0 0x00000080 0x00000080 NONE NONE    0     vector.TIM3_COMPA
  0 0x00000084 0x00000084 NONE NONE    0     vector.TIM3_COMPB
  0 0x00000088 0x00000088 NONE NONE    0     vector.TIM3_COMPC
  0 0x0000008c 0x0000008c NONE NONE    0     vector.TIM3_OVF
  0 0x00000090 0x00000090 NONE NONE    0     vector.USART1_RXC
  0 0x000000f6 0x000000f6 NONE NONE    0     handler.USART1_RXC
  0 0x00000094 0x00000094 NONE NONE    0     vector.USART1_UDRE
  0 0x00000098 0x00000098 NONE NONE    0     vector.USART1_TXC
  0 0x0000009c 0x0000009c NONE NONE    0     vector.TWI
  0 0x000000a0 0x000000a0 NONE NONE    0     vector.SPM_RDY
  0 0x000000a4 0x000000a4 NONE NONE    0     vector.TIM4_CAPT
  0 0x000000a8 0x000000a8 NONE NONE    0     vector.TIM4_COMPA
  0 0x000000ac 0x000000ac NONE NONE    0     vector.TIM4_COMPB
  0 0x000000b0 0x000000b0 NONE NONE    0     vector.TIM4_COMPC
  0 0x000000b4 0x000000b4 NONE NONE    0     vector.TIM4_OVF
  0 0x000000b8 0x000000b8 NONE NONE    0     vector.TIM5_CAPT
  0 0x000000bc 0x000000bc NONE NONE    0     vector.TIM5_COMPA
  0 0x000000c0 0x000000c0 NONE NONE    0     vector.TIM5_COMPB
  0 0x000000c4 0x000000c4 NONE NONE    0     vector.TIM5_COMPC
  0 0x000000c8 0x000000c8 NONE NONE    0     vector.TIM5_OVF
  0 0x000000cc 0x000000cc NONE NONE    0     vector.USART2_RXC
  0 0x000000d0 0x000000d0 NONE NONE    0     vector.USART2_UDRE
  0 0x000000d4 0x000000d4 NONE NONE    0     vector.USART2_TXC
  0 0x000000d8 0x000000d8 NONE NONE    0     vector.USART3_RXC
  0 0x000000dc 0x000000dc NONE NONE    0     vector.USART3_UDRE
  0 0x000000e0 0x000000e0 NONE NONE    0     vector.USART3_TXC

[Sections]
paddr size vaddr vsize align perm name type flags 
--------------------------------------------------

[Memory]
name size address flags mirror 
-------------------------------

[Strings]
paddr vaddr len size section type string 
-----------------------------------------

      addr size space   name                   realname           
------------------------------------------------------------------
0x00000000    1 symbols entry0                 entry0
0x00000000    0 symbols sym.vector.RESET       vector.RESET
0x00000004    0 symbols sym.vector.INT0        vector.INT0
0x00000008    0 symbols sym.vector.INT1        vector.INT1
0x0000000c    0 symbols sym.vector.INT2        vector.INT2
0x00000010    0 symbols sym.vector.INT3        vector.INT3
0x00000014    0 symbols sym.vector.INT4        vector.INT4
0x00000018    0 symbols sym.vector.INT5        vector.INT5
0x0000001c    0 symbols sym.vector.INT6        vector.INT6
0x00000020    0 symbols sym.vector.INT7        vector.INT7
0x00000024    0 symbols sym.vector.PCINT0      vector.PCINT0
0x00000028    0 symbols sym.vector.PCINT1      vector.PCINT1
0x0000002c    0 symbols sym.vector.PCINT2      vector.PCINT2
0x00000030    0 symbols sym.vector.WDT         vector.WDT
0x00000034    0 symbols sym.vector.TIM2_COMPA  vector.TIM2_COMPA
0x00000038    0 symbols sym.vector.TIM2_COMPB  vector.TIM2_COMPB
0x0000003c    0 symbols sym.vector.TIM2_OVF    vector.TIM2_OVF
0x00000040    0 symbols sym.vector.TIM1_CAPT   vector.TIM1_CAPT
0x00000044    0 symbols sym.vector.TIM1_COMPA  vector.TIM1_COMPA
0x00000048    0 symbols sym.vector.TIM1_COMPB  vector.TIM1_COMPB
0x0000004c    0 symbols sym.vector.TIM1_COMPC  vector.TIM1_COMPC
0x00000050    0 symbols sym.vector.TIM1_OVF    vector.TIM1_OVF
0x00000054    0 symbols sym.vector.TIM0_COMPA  vector.TIM0_COMPA
0x00000058    0 symbols sym.vector.TIM0_COMPB  vector.TIM0_COMPB
0x0000005c    0 symbols sym.vector.TIM0_OVF    vector.TIM0_OVF
0x00000060    0 symbols sym.vector.SPI_STC     vector.SPI_STC
0x00000064    0 symbols sym.vector.USART0_RXC  vector.USART0_RXC
0x00000068    0 symbols sym.vector.USART0_UDRE vector.USART0_UDRE
0x0000006c    0 symbols sym.vector.USART0_TXC  vector.USART0_TXC
0x00000070    0 symbols sym.vector.ANA_COMP    vector.ANA_COMP
0x00000074    0 symbols sym.vector.ADC         vector.ADC
0x00000078    0 symbols sym.vector.EE_RDY      vector.EE_RDY
0x0000007c    0 symbols sym.vector.TIM3_CAPT   vector.TIM3_CAPT
0x00000080    0 symbols sym.vector.TIM3_COMPA  vector.TIM3_COMPA
0x00000084    0 symbols sym.vector.TIM3_COMPB  vector.TIM3_COMPB
0x00000088    0 symbols sym.vector.TIM3_COMPC  vector.TIM3_COMPC
0x0000008c    0 symbols sym.vector.TIM3_OVF    vector.TIM3_OVF
0x00000090    0 symbols sym.vector.USART1_RXC  vector.USART1_RXC
0x00000094    0 symbols sym.vector.USART1_UDRE vector.USART1_UDRE
0x00000098    0 symbols sym.vector.USART1_TXC  vector.USART1_TXC
0x0000009c    0 symbols sym.vector.TWI         vector.TWI
0x000000a0    0 symbols sym.vector.SPM_RDY     vector.SPM_RDY
0x000000a4    0 symbols sym.vector.TIM4_CAPT   vector.TIM4_CAPT
0x000000a8    0 symbols sym.vector.TIM4_COMPA  vector.TIM4_COMPA
0x000000ac    0 symbols sym.vector.TIM4_COMPB  vector.TIM4_COMPB
0x000000b0    0 symbols sym.vector.TIM4_COMPC  vector.TIM4_COMPC
0x000000b4    0 symbols sym.vector.TIM4_OVF    vector.TIM4_OVF
0x000000b8    0 symbols sym.vector.TIM5_CAPT   vector.TIM5_CAPT
0x000000bc    0 symbols sym.vector.TIM5_COMPA  vector.TIM5_COMPA
0x000000c0    0 symbols sym.vector.TIM5_COMPB  vector.TIM5_COMPB
0x000000c4    0 symbols sym.vector.TIM5_COMPC  vector.TIM5_COMPC
0x000000c8    0 symbols sym.vector.TIM5_OVF    vector.TIM5_OVF
0x000000cc    0 symbols sym.vector.USART2_RXC  vector.USART2_RXC
0x000000d0    0 symbols sym.vector.USART2_UDRE vector.USART2_UDRE
0x000000d4    0 symbols sym.vector.USART2_TXC  vector.USART2_TXC
0x000000d8    0 symbols sym.vector.USART3_RXC  vector.USART3_RXC
0x000000dc    0 symbols sym.vector.USART3_UDRE vector.USART3_UDRE
0x000000e0    0 symbols sym.vector.USART3_TXC  vector.USART3_TXC
0x000000f6    0 symbols sym.handler.USART1_RXC handler.USART1_RXC
0x00000248    0 symbols sym.handler.INT0       handler.INT0
0x00001cf0  256 symbols main                   main
0x00001cf0    1 symbols entry.init0            entry.init0
0x00001cf0    0 symbols sym.handler.RESET      handler.RESET
            ;-- entry0:
            ;-- vector.RESET:
        ,=< 0x00000000      jmp   main
        |   ;-- vector.INT0:
        |   0x00000004      rcall sym.handler.INT0
        |   0x00000006      invalid
        |   ;-- vector.INT1:
        |   0x00000008      rcall sym.handler.INT0
        |   0x0000000a      invalid
        |   ;-- vector.INT2:
        |   0x0000000c      rcall sym.handler.INT0
        |   0x0000000e      invalid
        |   ;-- vector.INT3:
        |   0x00000010      rcall sym.handler.INT0
        |   0x00000012      invalid
        |   ;-- vector.INT4:
        |   0x00000014      rcall sym.handler.INT0
        |   0x00000016      invalid
        |   ;-- vector.INT5:
        |   0x00000018      rcall sym.handler.INT0
        |   0x0000001a      invalid
        |   ;-- vector.INT6:
        |   0x0000001c      rcall sym.handler.INT0
        |   0x0000001e      invalid
        |   ;-- vector.INT7:
        |   0x00000020      rcall sym.handler.INT0
        |   0x00000022      invalid
        |   ;-- vector.PCINT0:
        |   0x00000024      rcall sym.handler.INT0
        |   0x00000026      invalid
        |   ;-- vector.PCINT1:
        |   0x00000028      rcall sym.handler.INT0
        |   0x0000002a      invalid
        |   ;-- vector.PCINT2:
        |   0x0000002c      rcall sym.handler.INT0
        |   0x0000002e      invalid
        |   ;-- vector.WDT:
        |   0x00000030      rcall sym.handler.INT0
        |   0x00000032      invalid
        |   ;-- vector.TIM2_COMPA:
        |   0x00000034      rcall sym.handler.INT0
        |   0x00000036      invalid
        |   ;-- vector.TIM2_COMPB:
        |   0x00000038      rcall sym.handler.INT0
        |   0x0000003a      invalid
        |   ;-- vector.TIM2_OVF:
        |   0x0000003c      rcall sym.handler.INT0
        |   0x0000003e      invalid
        |   ;-- vector.TIM1_CAPT:
        |   0x00000040      rcall sym.handler.INT0
        |   0x00000042      invalid
        |   ;-- vector.TIM1_COMPA:
        |   0x00000044      rcall sym.handler.INT0
        |   0x00000046      invalid
        |   ;-- vector.TIM1_COMPB:
        |   0x00000048      rcall sym.handler.INT0
        |   0x0000004a      invalid
        |   ;-- vector.TIM1_COMPC:
        |   0x0000004c      rcall sym.handler.INT0
        |   0x0000004e      invalid
        |   ;-- vector.TIM1_OVF:
        |   0x00000050      rcall sym.handler.INT0
        |   0x00000052      invalid
        |   ;-- vector.TIM0_COMPA:
        |   0x00000054      rcall sym.handler.INT0
        |   0x00000056      invalid
        |   ;-- vector.TIM0_COMPB:
        |   0x00000058      rcall sym.handler.INT0
        |   0x0000005a      invalid
        |   ;-- vector.TIM0_OVF:
        |   0x0000005c      rcall sym.handler.INT0
        |   0x0000005e      invalid
        |   ;-- vector.SPI_STC:
        |   0x00000060      rcall sym.handler.INT0
        |   0x00000062      invalid
        |   ;-- vector.USART0_RXC:
        |   0x00000064      rcall sym.handler.INT0
        |   0x00000066      invalid
        |   ;-- vector.USART0_UDRE:
        |   0x00000068      rcall sym.handler.INT0
        |   0x0000006a      invalid
        |   ;-- vector.USART0_TXC:
        |   0x0000006c      rcall sym.handler.INT0
        |   0x0000006e      invalid
        |   ;-- vector.ANA_COMP:
        |   0x00000070      rcall sym.handler.INT0
        |   0x00000072      invalid
        |   ;-- vector.ADC:
        |   0x00000074      rcall sym.handler.INT0
        |   0x00000076      invalid
        |   ;-- vector.EE_RDY:
        |   0x00000078      rcall sym.handler.INT0
        |   0x0000007a      invalid
        |   ;-- vector.TIM3_CAPT:
        |   0x0000007c      rcall sym.handler.INT0
        |   0x0000007e      invalid
        |   ;-- vector.TIM3_COMPA:
        |   0x00000080      rcall sym.handler.INT0
        |   0x00000082      invalid
        |   ;-- vector.TIM3_COMPB:
        |   0x00000084      rcall sym.handler.INT0
        |   0x00000086      invalid
        |   ;-- vector.TIM3_COMPC:
        |   0x00000088      rcall sym.handler.INT0
        |   0x0000008a      invalid
        |   ;-- vector.TIM3_OVF:
        |   0x0000008c      rcall sym.handler.INT0
        |   0x0000008e      invalid
        |   ;-- vector.USART1_RXC:
       ,==< 0x00000090      rjmp  sym.handler.USART1_RXC
       ||   0x00000092      invalid
       ||   ;-- vector.USART1_UDRE:
       ||   0x00000094      rcall sym.handler.INT0
       ||   0x00000096      invalid
       ||   ;-- vector.USART1_TXC:
       ||   0x00000098      rcall sym.handler.INT0
       ||   0x0000009a      invalid
       ||   ;-- vector.TWI:
       ||   0x0000009c      rcall sym.handler.INT0
       ||   0x0000009e      invalid
       ||   ;-- vector.SPM_RDY:
       ||   0x000000a0      rcall sym.handler.INT0
       ||   0x000000a2      invalid
       ||   ;-- vector.TIM4_CAPT:
       ||   0x000000a4      rcall sym.handler.INT0
       ||   0x000000a6      invalid
       ||   ;-- vector.TIM4_COMPA:
       ||   0x000000a8      rcall sym.handler.INT0
       ||   0x000000aa      invalid
       ||   ;-- vector.TIM4_COMPB:
       ||   0x000000ac      rcall sym.handler.INT0
       ||   0x000000ae      invalid
       ||   ;-- vector.TIM4_COMPC:
       ||   0x000000b0      rcall sym.handler.INT0
       ||   0x000000b2      invalid
       ||   ;-- vector.TIM4_OVF:
       ||   0x000000b4      rcall sym.handler.INT0
       ||   0x000000b6      invalid
       ||   ;-- vector.TIM5_CAPT:
       ||   0x000000b8      rcall sym.handler.INT0
       ||   0x000000ba      invalid
       ||   ;-- vector.TIM5_COMPA:
       ||   0x000000bc      rcall sym.handler.INT0
       ||   0x000000be      invalid
       ||   ;-- vector.TIM5_COMPB:
       ||   0x000000c0      rcall sym.handler.INT0
       ||   0x000000c2      invalid
       ||   ;-- vector.TIM5_COMPC:
       ||   0x000000c4      rcall sym.handler.INT0
       ||   0x000000c6      invalid
       ||   ;-- vector.TIM5_OVF:
       ||   0x000000c8      rcall sym.handler.INT0
       ||   0x000000ca      invalid
       ||   ;-- vector.USART2_RXC:
       ||   0x000000cc      rcall sym.handler.INT0
       ||   0x000000ce      invalid
       ||   ;-- vector.USART2_UDRE:
       ||   0x000000d0      rcall sym.handler.INT0
       ||   0x000000d2      invalid
       ||   ;-- vector.USART2_TXC:
       ||   0x000000d4      rcall sym.handler.INT0
       ||   0x000000d6      invalid
       ||   ;-- vector.USART3_RXC:
       ||   0x000000d8      rcall sym.handler.INT0
       ||   0x000000da      invalid
       ||   ;-- vector.USART3_UDRE:
       ||   0x000000dc      rcall sym.handler.INT0
       ||   0x000000de      invalid
       ||   ;-- vector.USART3_TXC:
       ||   0x000000e0      rcall sym.handler.INT0
       ||   0x000000e2      tst   r0
       ||   0x000000e4      cpse  r0, r0
       ||   0x000000e6      invalid
       ||   0x000000e8      invalid
       ||   0x000000ea      invalid
       ||   0x000000ec      subi  r20, 0x41
       ||   0x000000ee      ori   r22, 0x5d
       ||   0x000000f0      ori   r22, 0x17
EOF
RUN

NAME=ATmega16u4/32u4
FILE=ihex://bins/avr/ATmega32U4_8MHz_TKL.hex
CMDS=<<EOF
ia
flt
pd 60 @ 0
EOF
EXPECT=<<EOF
[Info]
arch     avr
cpu      ATmega32u4
features N/A
baddr    ----------
binsz    0x000065a0
bintype  N/A
bits     8
class    N/A
compiler N/A
dbg_file N/A
endian   LE
hdr.csum N/A
guid     N/A
intrp    N/A
laddr    0x00000000
lang     N/A
machine  ATmega16u4/32u4
maxopsz  4
minopsz  2
os       avr usermode
cc       N/A
pcalign  2
rpath    N/A
subsys   
stripped false
havecode true
va       false
static   true
linenum  false
lsyms    false
canary   false
pie      false
relrocs  false
nx       false

[Imports]
nth vaddr bind type lib name 
-----------------------------

[Entries]
     vaddr      paddr     hvaddr      haddr type    
----------------------------------------------------
0x00000000 0x00000000 ---------- ---------- program
0x0000260e 0x0000260e 0x0000260e 0x0000260e init

[Exports]
nth paddr vaddr bind type size lib name 
----------------------------------------

[Classes]
address min max name super 
---------------------------

[Symbols]
nth      paddr      vaddr bind type size lib name               
----------------------------------------------------------------
  0 0x000026ae 0x000026ae NONE NONE    0     __bad_interrupt
  0 0x00000000 0x00000000 NONE NONE    0     vector.RESET
  0 0x0000260e 0x0000260e NONE NONE    0     handler.RESET
  0 0x00000004 0x00000004 NONE NONE    0     vector.EXT_INT0
  0 0x00000008 0x00000008 NONE NONE    0     vector.EXT_INT1
  0 0x0000000c 0x0000000c NONE NONE    0     vector.EXT_INT2
  0 0x00000010 0x00000010 NONE NONE    0     vector.EXT_INT3
  0 0x00000014 0x00000014 NONE NONE    0     vector.Reserved_6
  0 0x00000018 0x00000018 NONE NONE    0     vector.Reserved_7
  0 0x0000001c 0x0000001c NONE NONE    0     vector.INT6
  0 0x00000020 0x00000020 NONE NONE    0     vector.Reserved_9
  0 0x00000024 0x00000024 NONE NONE    0     vector.PCINT0
  0 0x00000028 0x00000028 NONE NONE    0     vector.GEN_USB
  0 0x00005b7e 0x00005b7e NONE NONE    0     handler.GEN_USB
  0 0x0000002c 0x0000002c NONE NONE    0     vector.END_USB
  0 0x00000030 0x00000030 NONE NONE    0     vector.WDT
  0 0x00004792 0x00004792 NONE NONE    0     handler.WDT
  0 0x00000034 0x00000034 NONE NONE    0     vector.Reserved_14
  0 0x00000038 0x00000038 NONE NONE    0     vector.Reserved_15
  0 0x0000003c 0x0000003c NONE NONE    0     vector.Reserved_16
  0 0x00000040 0x00000040 NONE NONE    0     vector.TIM1_CAPT
  0 0x00000044 0x00000044 NONE NONE    0     vector.TIM1_COMPA
  0 0x00005162 0x00005162 NONE NONE    0     handler.TIM1_COMPA
  0 0x00000048 0x00000048 NONE NONE    0     vector.TIM1_COMPB
  0 0x0000004c 0x0000004c NONE NONE    0     vector.TIM1_COMPC
  0 0x00000050 0x00000050 NONE NONE    0     vector.TIM1_OVF
  0 0x00000054 0x00000054 NONE NONE    0     vector.TIM0_COMPA
  0 0x00000058 0x00000058 NONE NONE    0     vector.TIM0_COMPB
  0 0x0000005c 0x0000005c NONE NONE    0     vector.TIM0_OVF
  0 0x00000060 0x00000060 NONE NONE    0     vector.SPI
  0 0x00000064 0x00000064 NONE NONE    0     vector.USART1_RXC
  0 0x00000068 0x00000068 NONE NONE    0     vector.USART1_UDRE
  0 0x0000006c 0x0000006c NONE NONE    0     vector.USART1_TXC
  0 0x00000070 0x00000070 NONE NONE    0     vector.ANA_COMP
  0 0x00000074 0x00000074 NONE NONE    0     vector.ADC
  0 0x00000078 0x00000078 NONE NONE    0     vector.EE_RDY
  0 0x0000007c 0x0000007c NONE NONE    0     vector.TIM3_CAPT
  0 0x00000080 0x00000080 NONE NONE    0     vector.TIM3_COMPA
  0 0x00000084 0x00000084 NONE NONE    0     vector.TIM3_COMPB
  0 0x00000088 0x00000088 NONE NONE    0     vector.TIM3_COMPC
  0 0x0000008c 0x0000008c NONE NONE    0     vector.TIM3_OVF
  0 0x00000090 0x00000090 NONE NONE    0     vector.TWI
  0 0x00000094 0x00000094 NONE NONE    0     vector.SPM_RDY
  0 0x00000098 0x00000098 NONE NONE    0     vector.TIM4_COMPA
  0 0x0000009c 0x0000009c NONE NONE    0     vector.TIM4_COMPB
  0 0x000000a0 0x000000a0 NONE NONE    0     vector.TIM4_COMPD
  0 0x000000a4 0x000000a4 NONE NONE    0     vector.TIM4_OVF
  0 0x000000a8 0x000000a8 NONE NONE    0     vector.TIM4_FPF

[Sections]
paddr size vaddr vsize align perm name type flags 
--------------------------------------------------

[Memory]
name size address flags mirror 
-------------------------------

[Strings]
paddr vaddr len size section type string 
-----------------------------------------

      addr size space   name                   realname           
------------------------------------------------------------------
0x00000000    1 symbols entry0                 entry0
0x00000000    0 symbols sym.vector.RESET       vector.RESET
0x00000004    0 symbols sym.vector.EXT_INT0    vector.EXT_INT0
0x00000008    0 symbols sym.vector.EXT_INT1    vector.EXT_INT1
0x0000000c    0 symbols sym.vector.EXT_INT2    vector.EXT_INT2
0x00000010    0 symbols sym.vector.EXT_INT3    vector.EXT_INT3
0x00000014    0 symbols sym.vector.Reserved_6  vector.Reserved_6
0x00000018    0 symbols sym.vector.Reserved_7  vector.Reserved_7
0x0000001c    0 symbols sym.vector.INT6        vector.INT6
0x00000020    0 symbols sym.vector.Reserved_9  vector.Reserved_9
0x00000024    0 symbols sym.vector.PCINT0      vector.PCINT0
0x00000028    0 symbols sym.vector.GEN_USB     vector.GEN_USB
0x0000002c    0 symbols sym.vector.END_USB     vector.END_USB
0x00000030    0 symbols sym.vector.WDT         vector.WDT
0x00000034    0 symbols sym.vector.Reserved_14 vector.Reserved_14
0x00000038    0 symbols sym.vector.Reserved_15 vector.Reserved_15
0x0000003c    0 symbols sym.vector.Reserved_16 vector.Reserved_16
0x00000040    0 symbols sym.vector.TIM1_CAPT   vector.TIM1_CAPT
0x00000044    0 symbols sym.vector.TIM1_COMPA  vector.TIM1_COMPA
0x00000048    0 symbols sym.vector.TIM1_COMPB  vector.TIM1_COMPB
0x0000004c    0 symbols sym.vector.TIM1_COMPC  vector.TIM1_COMPC
0x00000050    0 symbols sym.vector.TIM1_OVF    vector.TIM1_OVF
0x00000054    0 symbols sym.vector.TIM0_COMPA  vector.TIM0_COMPA
0x00000058    0 symbols sym.vector.TIM0_COMPB  vector.TIM0_COMPB
0x0000005c    0 symbols sym.vector.TIM0_OVF    vector.TIM0_OVF
0x00000060    0 symbols sym.vector.SPI         vector.SPI
0x00000064    0 symbols sym.vector.USART1_RXC  vector.USART1_RXC
0x00000068    0 symbols sym.vector.USART1_UDRE vector.USART1_UDRE
0x0000006c    0 symbols sym.vector.USART1_TXC  vector.USART1_TXC
0x00000070    0 symbols sym.vector.ANA_COMP    vector.ANA_COMP
0x00000074    0 symbols sym.vector.ADC         vector.ADC
0x00000078    0 symbols sym.vector.EE_RDY      vector.EE_RDY
0x0000007c    0 symbols sym.vector.TIM3_CAPT   vector.TIM3_CAPT
0x00000080    0 symbols sym.vector.TIM3_COMPA  vector.TIM3_COMPA
0x00000084    0 symbols sym.vector.TIM3_COMPB  vector.TIM3_COMPB
0x00000088    0 symbols sym.vector.TIM3_COMPC  vector.TIM3_COMPC
0x0000008c    0 symbols sym.vector.TIM3_OVF    vector.TIM3_OVF
0x00000090    0 symbols sym.vector.TWI         vector.TWI
0x00000094    0 symbols sym.vector.SPM_RDY     vector.SPM_RDY
0x00000098    0 symbols sym.vector.TIM4_COMPA  vector.TIM4_COMPA
0x0000009c    0 symbols sym.vector.TIM4_COMPB  vector.TIM4_COMPB
0x000000a0    0 symbols sym.vector.TIM4_COMPD  vector.TIM4_COMPD
0x000000a4    0 symbols sym.vector.TIM4_OVF    vector.TIM4_OVF
0x000000a8    0 symbols sym.vector.TIM4_FPF    vector.TIM4_FPF
0x0000260e  256 symbols main                   main
0x0000260e    1 symbols entry.init0            entry.init0
0x0000260e    0 symbols sym.handler.RESET      handler.RESET
0x000026ae    0 symbols sym.__bad_interrupt    __bad_interrupt
0x00004792    0 symbols sym.handler.WDT        handler.WDT
0x00005162    0 symbols sym.handler.TIM1_COMPA handler.TIM1_COMPA
0x00005b7e    0 symbols sym.handler.GEN_USB    handler.GEN_USB
            ;-- entry0:
            ;-- vector.RESET:
        ,=< 0x00000000      jmp   main
        |   ;-- vector.EXT_INT0:
       ,==< 0x00000004      jmp   sym.__bad_interrupt
       ||   ;-- vector.EXT_INT1:
      ,===< 0x00000008      jmp   sym.__bad_interrupt
      |||   ;-- vector.EXT_INT2:
     ,====< 0x0000000c      jmp   sym.__bad_interrupt
     ||||   ;-- vector.EXT_INT3:
    ,=====< 0x00000010      jmp   sym.__bad_interrupt
    |||||   ;-- vector.Reserved_6:
   ,======< 0x00000014      jmp   sym.__bad_interrupt
   ||||||   ;-- vector.Reserved_7:
  ,=======< 0x00000018      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.INT6:
  ========< 0x0000001c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.Reserved_9:
  ========< 0x00000020      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.PCINT0:
  ========< 0x00000024      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.GEN_USB:
  ========< 0x00000028      jmp   sym.handler.GEN_USB
  |||||||   ;-- vector.END_USB:
  ========< 0x0000002c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.WDT:
  ========< 0x00000030      jmp   sym.handler.WDT
  |||||||   ;-- vector.Reserved_14:
  ========< 0x00000034      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.Reserved_15:
  ========< 0x00000038      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.Reserved_16:
  ========< 0x0000003c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_CAPT:
  ========< 0x00000040      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_COMPA:
  ========< 0x00000044      jmp   sym.handler.TIM1_COMPA
  |||||||   ;-- vector.TIM1_COMPB:
  ========< 0x00000048      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_COMPC:
  ========< 0x0000004c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_OVF:
  ========< 0x00000050      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM0_COMPA:
  ========< 0x00000054      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM0_COMPB:
  ========< 0x00000058      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM0_OVF:
  ========< 0x0000005c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.SPI:
  ========< 0x00000060      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART1_RXC:
  ========< 0x00000064      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART1_UDRE:
  ========< 0x00000068      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART1_TXC:
  ========< 0x0000006c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.ANA_COMP:
  ========< 0x00000070      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.ADC:
  ========< 0x00000074      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.EE_RDY:
  ========< 0x00000078      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM3_CAPT:
  ========< 0x0000007c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM3_COMPA:
  ========< 0x00000080      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM3_COMPB:
  ========< 0x00000084      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM3_COMPC:
  ========< 0x00000088      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM3_OVF:
  ========< 0x0000008c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TWI:
  ========< 0x00000090      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.SPM_RDY:
  ========< 0x00000094      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM4_COMPA:
  ========< 0x00000098      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM4_COMPB:
  ========< 0x0000009c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM4_COMPD:
  ========< 0x000000a0      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM4_OVF:
  ========< 0x000000a4      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM4_FPF:
  ========< 0x000000a8      jmp   sym.__bad_interrupt
  |||||||   0x000000ac      sub   r15, r17
  |||||||   0x000000ae      cp    r5, r17
  |||||||   0x000000b0      cp    r5, r23
  |||||||   0x000000b2      cp    r7, r25
  |||||||   0x000000b4      cp    r7, r31
  |||||||   0x000000b6      cp    r25, r28
  |||||||   0x000000b8      cp    r31, r20
  |||||||   0x000000ba      sub   r2, r2
  |||||||   0x000000bc      sub   r9, r13
  |||||||   0x000000be      sub   r17, r12
  |||||||   0x000000c0      sub   r21, r4
  |||||||   0x000000c2      sub   r2, r23
  |||||||   0x000000c4      sub   r7, r22
  |||||||   0x000000c6      sub   r9, r26
  |||||||   0x000000c8      cp    r10, r25
  |||||||   0x000000ca      cp    r12, r27
  |||||||   0x000000cc      cp    r14, r21
EOF
RUN

NAME=ATmega88/168
FILE=ihex://bins/avr/usbasp.atmega88.2018-06-25.hex
CMDS=<<EOF
ia
flt
pd 32 @ 0
EOF
EXPECT=<<EOF
[Info]
arch     avr
cpu      ATmega168
features N/A
baddr    ----------
binsz    0x00001236
bintype  N/A
bits     8
class    N/A
compiler N/A
dbg_file N/A
endian   LE
hdr.csum N/A
guid     N/A
intrp    N/A
laddr    0x00000000
lang     N/A
machine  ATmega88/168
maxopsz  4
minopsz  2
os       avr usermode
cc       N/A
pcalign  2
rpath    N/A
subsys   
stripped false
havecode true
va       false
static   true
linenum  false
lsyms    false
canary   false
pie      false
relrocs  false
nx       false

[Imports]
nth vaddr bind type lib name 
-----------------------------

[Entries]
     vaddr      paddr     hvaddr      haddr type    
----------------------------------------------------
0x00000000 0x00000000 ---------- ---------- program
0x00000098 0x00000098 0x00000098 0x00000098 init

[Exports]
nth paddr vaddr bind type size lib name 
----------------------------------------

[Classes]
address min max name super 
---------------------------

[Symbols]
nth      paddr      vaddr bind type size lib name              
---------------------------------------------------------------
  0 0x000000ce 0x000000ce NONE NONE    0     __bad_interrupt
  0 0x00000000 0x00000000 NONE NONE    0     vector.RESET
  0 0x00000098 0x00000098 NONE NONE    0     handler.RESET
  0 0x00000002 0x00000002 NONE NONE    0     vector.EXT_INT0
  0 0x00000372 0x00000372 NONE NONE    0     handler.EXT_INT0
  0 0x00000004 0x00000004 NONE NONE    0     vector.EXT_INT1
  0 0x00000006 0x00000006 NONE NONE    0     vector.PCINT0
  0 0x00000008 0x00000008 NONE NONE    0     vector.PCINT1
  0 0x0000000a 0x0000000a NONE NONE    0     vector.PCINT2
  0 0x0000000c 0x0000000c NONE NONE    0     vector.WDT
  0 0x0000000e 0x0000000e NONE NONE    0     vector.TIM2_COMPA
  0 0x00000010 0x00000010 NONE NONE    0     vector.TIM2_COMPB
  0 0x00000012 0x00000012 NONE NONE    0     vector.TIM2_OVF
  0 0x00000014 0x00000014 NONE NONE    0     vector.TIM1_CAPT
  0 0x00000016 0x00000016 NONE NONE    0     vector.TIM1_COMPA
  0 0x00000018 0x00000018 NONE NONE    0     vector.TIM1_COMPB
  0 0x0000001a 0x0000001a NONE NONE    0     vector.TIM1_OVF
  0 0x0000001c 0x0000001c NONE NONE    0     vector.TIM0_COMPA
  0 0x0000001e 0x0000001e NONE NONE    0     vector.TIM0_COMPB
  0 0x00000020 0x00000020 NONE NONE    0     vector.TIM0_OVF
  0 0x00000022 0x00000022 NONE NONE    0     vector.SPI_STC
  0 0x00000024 0x00000024 NONE NONE    0     vector.USART_RXC
  0 0x00000026 0x00000026 NONE NONE    0     vector.USART_UDRE
  0 0x00000028 0x00000028 NONE NONE    0     vector.USART_TXC
  0 0x0000002a 0x0000002a NONE NONE    0     vector.ADC
  0 0x0000002c 0x0000002c NONE NONE    0     vector.EE_RDY
  0 0x0000002e 0x0000002e NONE NONE    0     vector.ANA_COMP
  0 0x00000030 0x00000030 NONE NONE    0     vector.TWI
  0 0x00000032 0x00000032 NONE NONE    0     vector.SPM_RDY

[Sections]
paddr size vaddr vsize align perm name type flags 
--------------------------------------------------

[Memory]
name size address flags mirror 
-------------------------------

[Strings]
paddr vaddr len size section type string 
-----------------------------------------

      addr size space   name                  realname          
----------------------------------------------------------------
0x00000000    1 symbols entry0                entry0
0x00000000    0 symbols sym.vector.RESET      vector.RESET
0x00000002    0 symbols sym.vector.EXT_INT0   vector.EXT_INT0
0x00000004    0 symbols sym.vector.EXT_INT1   vector.EXT_INT1
0x00000006    0 symbols sym.vector.PCINT0     vector.PCINT0
0x00000008    0 symbols sym.vector.PCINT1     vector.PCINT1
0x0000000a    0 symbols sym.vector.PCINT2     vector.PCINT2
0x0000000c    0 symbols sym.vector.WDT        vector.WDT
0x0000000e    0 symbols sym.vector.TIM2_COMPA vector.TIM2_COMPA
0x00000010    0 symbols sym.vector.TIM2_COMPB vector.TIM2_COMPB
0x00000012    0 symbols sym.vector.TIM2_OVF   vector.TIM2_OVF
0x00000014    0 symbols sym.vector.TIM1_CAPT  vector.TIM1_CAPT
0x00000016    0 symbols sym.vector.TIM1_COMPA vector.TIM1_COMPA
0x00000018    0 symbols sym.vector.TIM1_COMPB vector.TIM1_COMPB
0x0000001a    0 symbols sym.vector.TIM1_OVF   vector.TIM1_OVF
0x0000001c    0 symbols sym.vector.TIM0_COMPA vector.TIM0_COMPA
0x0000001e    0 symbols sym.vector.TIM0_COMPB vector.TIM0_COMPB
0x00000020    0 symbols sym.vector.TIM0_OVF   vector.TIM0_OVF
0x00000022    0 symbols sym.vector.SPI_STC    vector.SPI_STC
0x00000024    0 symbols sym.vector.USART_RXC  vector.USART_RXC
0x00000026    0 symbols sym.vector.USART_UDRE vector.USART_UDRE
0x00000028    0 symbols sym.vector.USART_TXC  vector.USART_TXC
0x0000002a    0 symbols sym.vector.ADC        vector.ADC
0x0000002c    0 symbols sym.vector.EE_RDY     vector.EE_RDY
0x0000002e    0 symbols sym.vector.ANA_COMP   vector.ANA_COMP
0x00000030    0 symbols sym.vector.TWI        vector.TWI
0x00000032    0 symbols sym.vector.SPM_RDY    vector.SPM_RDY
0x00000098  256 symbols main                  main
0x00000098    1 symbols entry.init0           entry.init0
0x00000098    0 symbols sym.handler.RESET     handler.RESET
0x000000ce    0 symbols sym.__bad_interrupt   __bad_interrupt
0x00000372    0 symbols sym.handler.EXT_INT0  handler.EXT_INT0
            ;-- entry0:
            ;-- vector.RESET:
        ,=< 0x00000000      rjmp  0x98
        |   ;-- vector.EXT_INT0:
       ,==< 0x00000002      rjmp  sym.handler.EXT_INT0
       ||   ;-- vector.EXT_INT1:
      ,===< 0x00000004      rjmp  sym.__bad_interrupt
      |||   ;-- vector.PCINT0:
     ,====< 0x00000006      rjmp  sym.__bad_interrupt
     ||||   ;-- vector.PCINT1:
    ,=====< 0x00000008      rjmp  sym.__bad_interrupt
    |||||   ;-- vector.PCINT2:
   ,======< 0x0000000a      rjmp  sym.__bad_interrupt
   ||||||   ;-- vector.WDT:
  ,=======< 0x0000000c      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM2_COMPA:
  ========< 0x0000000e      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM2_COMPB:
  ========< 0x00000010      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM2_OVF:
  ========< 0x00000012      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_CAPT:
  ========< 0x00000014      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_COMPA:
  ========< 0x00000016      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_COMPB:
  ========< 0x00000018      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_OVF:
  ========< 0x0000001a      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM0_COMPA:
  ========< 0x0000001c      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM0_COMPB:
  ========< 0x0000001e      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM0_OVF:
  ========< 0x00000020      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.SPI_STC:
  ========< 0x00000022      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.USART_RXC:
  ========< 0x00000024      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.USART_UDRE:
  ========< 0x00000026      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.USART_TXC:
  ========< 0x00000028      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.ADC:
  ========< 0x0000002a      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.EE_RDY:
  ========< 0x0000002c      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.ANA_COMP:
  ========< 0x0000002e      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TWI:
  ========< 0x00000030      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.SPM_RDY:
  ========< 0x00000032      rjmp  sym.__bad_interrupt
  |||||||   0x00000034      muls  r16, r25
  |||||||   0x00000036      invalid
  |||||||   0x00000038      movw  r0, r2
  |||||||   0x0000003a      ldd   r0, Z+32
  |||||||   0x0000003c      sbc   r17, r9
  |||||||   0x0000003e      invalid
EOF
RUN


NAME=ATmega88 (neg jump)
FILE=ihex://bins/avr/ATmega88_neg_rjmp.hex
CMDS=<<EOF
ia
flt
pd 30 @ 0
EOF
EXPECT=<<EOF
[Info]
arch     avr
cpu      ATmega168
features N/A
baddr    ----------
binsz    0x00830001
bintype  N/A
bits     8
class    N/A
compiler N/A
dbg_file N/A
endian   LE
hdr.csum N/A
guid     N/A
intrp    N/A
laddr    0x00000000
lang     N/A
machine  ATmega88/168
maxopsz  4
minopsz  2
os       avr usermode
cc       N/A
pcalign  2
rpath    N/A
subsys   
stripped false
havecode true
va       false
static   true
linenum  false
lsyms    false
canary   false
pie      false
relrocs  false
nx       false

[Imports]
nth vaddr bind type lib name 
-----------------------------

[Entries]
             vaddr              paddr             hvaddr              haddr type    
------------------------------------------------------------------------------------
        0x00000000         0x00000000         ----------         ---------- program
0xffffffffffffff3a 0xffffffffffffff3a 0xffffffffffffff3a 0xffffffffffffff3a init

[Exports]
nth paddr vaddr bind type size lib name 
----------------------------------------

[Classes]
address min max name super 
---------------------------

[Symbols]
nth              paddr              vaddr bind type size lib name              
-------------------------------------------------------------------------------
  0         0x00000000         0x00000000 NONE NONE    0     vector.RESET
  0 0xffffffffffffff3a 0xffffffffffffff3a NONE NONE    0     handler.RESET
  0         0x00000002         0x00000002 NONE NONE    0     vector.EXT_INT0
  0         0x00000004         0x00000004 NONE NONE    0     vector.EXT_INT1
  0         0x00000006         0x00000006 NONE NONE    0     vector.PCINT0
  0         0x00000008         0x00000008 NONE NONE    0     vector.PCINT1
  0         0x0000000a         0x0000000a NONE NONE    0     vector.PCINT2
  0         0x0000000c         0x0000000c NONE NONE    0     vector.WDT
  0         0x0000000e         0x0000000e NONE NONE    0     vector.TIM2_COMPA
  0         0x00000010         0x00000010 NONE NONE    0     vector.TIM2_COMPB
  0         0x00000012         0x00000012 NONE NONE    0     vector.TIM2_OVF
  0         0x00000014         0x00000014 NONE NONE    0     vector.TIM1_CAPT
  0         0x00000016         0x00000016 NONE NONE    0     vector.TIM1_COMPA
  0         0x00000018         0x00000018 NONE NONE    0     vector.TIM1_COMPB
  0         0x0000001a         0x0000001a NONE NONE    0     vector.TIM1_OVF
  0         0x0000001c         0x0000001c NONE NONE    0     vector.TIM0_COMPA
  0         0x0000001e         0x0000001e NONE NONE    0     vector.TIM0_COMPB
  0         0x00000020         0x00000020 NONE NONE    0     vector.TIM0_OVF
  0         0x00000022         0x00000022 NONE NONE    0     vector.SPI_STC
  0         0x00000024         0x00000024 NONE NONE    0     vector.USART_RXC
  0         0x00000026         0x00000026 NONE NONE    0     vector.USART_UDRE
  0         0x00000028         0x00000028 NONE NONE    0     vector.USART_TXC
  0         0x0000002a         0x0000002a NONE NONE    0     vector.ADC
  0         0x0000002c         0x0000002c NONE NONE    0     vector.EE_RDY
  0         0x0000002e         0x0000002e NONE NONE    0     vector.ANA_COMP
  0         0x00000030         0x00000030 NONE NONE    0     vector.TWI
  0         0x0000096a         0x0000096a NONE NONE    0     handler.TWI
  0         0x00000032         0x00000032 NONE NONE    0     vector.SPM_RDY

[Sections]
paddr size vaddr vsize align perm name type flags 
--------------------------------------------------

[Memory]
name size address flags mirror 
-------------------------------

[Strings]
paddr vaddr len size section type string 
-----------------------------------------

              addr size space   name                  realname          
------------------------------------------------------------------------
        0x00000000    1 symbols entry0                entry0
        0x00000000    0 symbols sym.vector.RESET      vector.RESET
        0x00000002    0 symbols sym.vector.EXT_INT0   vector.EXT_INT0
        0x00000004    0 symbols sym.vector.EXT_INT1   vector.EXT_INT1
        0x00000006    0 symbols sym.vector.PCINT0     vector.PCINT0
        0x00000008    0 symbols sym.vector.PCINT1     vector.PCINT1
        0x0000000a    0 symbols sym.vector.PCINT2     vector.PCINT2
        0x0000000c    0 symbols sym.vector.WDT        vector.WDT
        0x0000000e    0 symbols sym.vector.TIM2_COMPA vector.TIM2_COMPA
        0x00000010    0 symbols sym.vector.TIM2_COMPB vector.TIM2_COMPB
        0x00000012    0 symbols sym.vector.TIM2_OVF   vector.TIM2_OVF
        0x00000014    0 symbols sym.vector.TIM1_CAPT  vector.TIM1_CAPT
        0x00000016    0 symbols sym.vector.TIM1_COMPA vector.TIM1_COMPA
        0x00000018    0 symbols sym.vector.TIM1_COMPB vector.TIM1_COMPB
        0x0000001a    0 symbols sym.vector.TIM1_OVF   vector.TIM1_OVF
        0x0000001c    0 symbols sym.vector.TIM0_COMPA vector.TIM0_COMPA
        0x0000001e    0 symbols sym.vector.TIM0_COMPB vector.TIM0_COMPB
        0x00000020    0 symbols sym.vector.TIM0_OVF   vector.TIM0_OVF
        0x00000022    0 symbols sym.vector.SPI_STC    vector.SPI_STC
        0x00000024    0 symbols sym.vector.USART_RXC  vector.USART_RXC
        0x00000026    0 symbols sym.vector.USART_UDRE vector.USART_UDRE
        0x00000028    0 symbols sym.vector.USART_TXC  vector.USART_TXC
        0x0000002a    0 symbols sym.vector.ADC        vector.ADC
        0x0000002c    0 symbols sym.vector.EE_RDY     vector.EE_RDY
        0x0000002e    0 symbols sym.vector.ANA_COMP   vector.ANA_COMP
        0x00000030    0 symbols sym.vector.TWI        vector.TWI
        0x00000032    0 symbols sym.vector.SPM_RDY    vector.SPM_RDY
        0x0000096a    0 symbols sym.handler.TWI       handler.TWI
0xffffffffffffff3a  256 symbols main                  main
0xffffffffffffff3a    1 symbols entry.init0           entry.init0
0xffffffffffffff3a    0 symbols sym.handler.RESET     handler.RESET
            ;-- entry0:
            ;-- vector.RESET:
        ,=< 0x00000000      rjmp  main
        |   ;-- vector.EXT_INT0:
        |   0x00000002      reti
        |   ;-- vector.EXT_INT1:
        |   0x00000004      reti
        |   ;-- vector.PCINT0:
        |   0x00000006      reti
        |   ;-- vector.PCINT1:
        |   0x00000008      reti
        |   ;-- vector.PCINT2:
        |   0x0000000a      reti
        |   ;-- vector.WDT:
        |   0x0000000c      reti
        |   ;-- vector.TIM2_COMPA:
        |   0x0000000e      reti
        |   ;-- vector.TIM2_COMPB:
        |   0x00000010      reti
        |   ;-- vector.TIM2_OVF:
        |   0x00000012      reti
        |   ;-- vector.TIM1_CAPT:
        |   0x00000014      reti
        |   ;-- vector.TIM1_COMPA:
        |   0x00000016      reti
        |   ;-- vector.TIM1_COMPB:
        |   0x00000018      reti
        |   ;-- vector.TIM1_OVF:
        |   0x0000001a      reti
        |   ;-- vector.TIM0_COMPA:
        |   0x0000001c      reti
        |   ;-- vector.TIM0_COMPB:
        |   0x0000001e      reti
        |   ;-- vector.TIM0_OVF:
        |   0x00000020      reti
        |   ;-- vector.SPI_STC:
        |   0x00000022      reti
        |   ;-- vector.USART_RXC:
        |   0x00000024      reti
        |   ;-- vector.USART_UDRE:
        |   0x00000026      reti
        |   ;-- vector.USART_TXC:
        |   0x00000028      reti
        |   ;-- vector.ADC:
        |   0x0000002a      reti
        |   ;-- vector.EE_RDY:
        |   0x0000002c      reti
        |   ;-- vector.ANA_COMP:
        |   0x0000002e      reti
        |   ;-- vector.TWI:
        ,=< 0x00000030      rjmp  sym.handler.TWI
       ||   ;-- vector.SPM_RDY:
       ||   0x00000032      reti
       ||   0x00000034      muls  r29, r16
       ||   0x00000036      movw  r22, r4
       ||   0x00000038      nop
       ||   0x0000003a      invalid
EOF
RUN

NAME=ATmega328p
FILE=ihex://bins/avr/grbl_0_51_atmega328p_16mhz_9600.hex
CMDS=<<EOF
ia
flt
pd 30 @ 0
EOF
EXPECT=<<EOF
[Info]
arch     avr
cpu      ATmega328p
features N/A
baddr    ----------
binsz    0x000033ea
bintype  N/A
bits     8
class    N/A
compiler N/A
dbg_file N/A
endian   LE
hdr.csum N/A
guid     N/A
intrp    N/A
laddr    0x00000000
lang     N/A
machine  ATmega328p
maxopsz  4
minopsz  2
os       avr usermode
cc       N/A
pcalign  2
rpath    N/A
subsys   
stripped false
havecode true
va       false
static   true
linenum  false
lsyms    false
canary   false
pie      false
relrocs  false
nx       false

[Imports]
nth vaddr bind type lib name 
-----------------------------

[Entries]
     vaddr      paddr     hvaddr      haddr type    
----------------------------------------------------
0x00000000 0x00000000 ---------- ---------- program
0x00000280 0x00000280 0x00000280 0x00000280 init

[Exports]
nth paddr vaddr bind type size lib name 
----------------------------------------

[Classes]
address min max name super 
---------------------------

[Symbols]
nth      paddr      vaddr bind type size lib name               
----------------------------------------------------------------
  0 0x000002ba 0x000002ba NONE NONE    0     __bad_interrupt
  0 0x00000000 0x00000000 NONE NONE    0     vector.RESET
  0 0x00000280 0x00000280 NONE NONE    0     handler.RESET
  0 0x00000004 0x00000004 NONE NONE    0     vector.EXT_INT0
  0 0x00000008 0x00000008 NONE NONE    0     vector.EXT_INT1
  0 0x0000000c 0x0000000c NONE NONE    0     vector.PCINT0
  0 0x00000010 0x00000010 NONE NONE    0     vector.PCINT1
  0 0x00000014 0x00000014 NONE NONE    0     vector.PCINT2
  0 0x00000018 0x00000018 NONE NONE    0     vector.WDT
  0 0x0000001c 0x0000001c NONE NONE    0     vector.TIM2_COMPA
  0 0x00000020 0x00000020 NONE NONE    0     vector.TIM2_COMPB
  0 0x00000024 0x00000024 NONE NONE    0     vector.TIM2_OVF
  0 0x00001c84 0x00001c84 NONE NONE    0     handler.TIM2_OVF
  0 0x00000028 0x00000028 NONE NONE    0     vector.TIM1_CAPT
  0 0x0000002c 0x0000002c NONE NONE    0     vector.TIM1_COMPA
  0 0x00001e2e 0x00001e2e NONE NONE    0     handler.TIM1_COMPA
  0 0x00000030 0x00000030 NONE NONE    0     vector.TIM1_COMPB
  0 0x00000034 0x00000034 NONE NONE    0     vector.TIM1_OVF
  0 0x00000038 0x00000038 NONE NONE    0     vector.TIM0_COMPA
  0 0x0000003c 0x0000003c NONE NONE    0     vector.TIM0_COMPB
  0 0x00000040 0x00000040 NONE NONE    0     vector.TIM0_OVF
  0 0x00000044 0x00000044 NONE NONE    0     vector.SPI_STC
  0 0x00000048 0x00000048 NONE NONE    0     vector.USART_RXC
  0 0x0000177a 0x0000177a NONE NONE    0     handler.USART_RXC
  0 0x0000004c 0x0000004c NONE NONE    0     vector.USART_UDRE
  0 0x00000050 0x00000050 NONE NONE    0     vector.USART_TXC
  0 0x00000054 0x00000054 NONE NONE    0     vector.ADC
  0 0x00000058 0x00000058 NONE NONE    0     vector.EE_RDY
  0 0x0000005c 0x0000005c NONE NONE    0     vector.ANA_COMP
  0 0x00000060 0x00000060 NONE NONE    0     vector.TWI
  0 0x00000064 0x00000064 NONE NONE    0     vector.SPM_RDY

[Sections]
paddr size vaddr vsize align perm name type flags 
--------------------------------------------------

[Memory]
name size address flags mirror 
-------------------------------

[Strings]
paddr vaddr len size section type string 
-----------------------------------------

      addr size space   name                   realname           
------------------------------------------------------------------
0x00000000    1 symbols entry0                 entry0
0x00000000    0 symbols sym.vector.RESET       vector.RESET
0x00000004    0 symbols sym.vector.EXT_INT0    vector.EXT_INT0
0x00000008    0 symbols sym.vector.EXT_INT1    vector.EXT_INT1
0x0000000c    0 symbols sym.vector.PCINT0      vector.PCINT0
0x00000010    0 symbols sym.vector.PCINT1      vector.PCINT1
0x00000014    0 symbols sym.vector.PCINT2      vector.PCINT2
0x00000018    0 symbols sym.vector.WDT         vector.WDT
0x0000001c    0 symbols sym.vector.TIM2_COMPA  vector.TIM2_COMPA
0x00000020    0 symbols sym.vector.TIM2_COMPB  vector.TIM2_COMPB
0x00000024    0 symbols sym.vector.TIM2_OVF    vector.TIM2_OVF
0x00000028    0 symbols sym.vector.TIM1_CAPT   vector.TIM1_CAPT
0x0000002c    0 symbols sym.vector.TIM1_COMPA  vector.TIM1_COMPA
0x00000030    0 symbols sym.vector.TIM1_COMPB  vector.TIM1_COMPB
0x00000034    0 symbols sym.vector.TIM1_OVF    vector.TIM1_OVF
0x00000038    0 symbols sym.vector.TIM0_COMPA  vector.TIM0_COMPA
0x0000003c    0 symbols sym.vector.TIM0_COMPB  vector.TIM0_COMPB
0x00000040    0 symbols sym.vector.TIM0_OVF    vector.TIM0_OVF
0x00000044    0 symbols sym.vector.SPI_STC     vector.SPI_STC
0x00000048    0 symbols sym.vector.USART_RXC   vector.USART_RXC
0x0000004c    0 symbols sym.vector.USART_UDRE  vector.USART_UDRE
0x00000050    0 symbols sym.vector.USART_TXC   vector.USART_TXC
0x00000054    0 symbols sym.vector.ADC         vector.ADC
0x00000058    0 symbols sym.vector.EE_RDY      vector.EE_RDY
0x0000005c    0 symbols sym.vector.ANA_COMP    vector.ANA_COMP
0x00000060    0 symbols sym.vector.TWI         vector.TWI
0x00000064    0 symbols sym.vector.SPM_RDY     vector.SPM_RDY
0x00000280  256 symbols main                   main
0x00000280    1 symbols entry.init0            entry.init0
0x00000280    0 symbols sym.handler.RESET      handler.RESET
0x000002ba    0 symbols sym.__bad_interrupt    __bad_interrupt
0x0000177a    0 symbols sym.handler.USART_RXC  handler.USART_RXC
0x00001c84    0 symbols sym.handler.TIM2_OVF   handler.TIM2_OVF
0x00001e2e    0 symbols sym.handler.TIM1_COMPA handler.TIM1_COMPA
            ;-- entry0:
            ;-- vector.RESET:
       ,==< 0x00000000      jmp   main
       |    ;-- vector.EXT_INT0:
      ,===< 0x00000004      jmp   sym.__bad_interrupt
      ||    ;-- vector.EXT_INT1:
     ,====< 0x00000008      jmp   sym.__bad_interrupt
     |||    ;-- vector.PCINT0:
    ,=====< 0x0000000c      jmp   sym.__bad_interrupt
    ||||    ;-- vector.PCINT1:
   ,======< 0x00000010      jmp   sym.__bad_interrupt
   |||||    ;-- vector.PCINT2:
  ,=======< 0x00000014      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.WDT:
  ========< 0x00000018      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.TIM2_COMPA:
  ========< 0x0000001c      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.TIM2_COMPB:
  ========< 0x00000020      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.TIM2_OVF:
  ========< 0x00000024      jmp   sym.handler.TIM2_OVF
  ||||||    ;-- vector.TIM1_CAPT:
  ========< 0x00000028      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.TIM1_COMPA:
  ========< 0x0000002c      jmp   sym.handler.TIM1_COMPA
  ||||||    ;-- vector.TIM1_COMPB:
  ========< 0x00000030      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.TIM1_OVF:
  ========< 0x00000034      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.TIM0_COMPA:
  ========< 0x00000038      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.TIM0_COMPB:
  ========< 0x0000003c      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.TIM0_OVF:
  ========< 0x00000040      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.SPI_STC:
  ========< 0x00000044      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.USART_RXC:
  ========< 0x00000048      jmp   sym.handler.USART_RXC
  ||||||    ;-- vector.USART_UDRE:
  ========< 0x0000004c      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.USART_TXC:
  ========< 0x00000050      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.ADC:
  ========< 0x00000054      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.EE_RDY:
  ========< 0x00000058      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.ANA_COMP:
  ========< 0x0000005c      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.TWI:
  ========< 0x00000060      jmp   sym.__bad_interrupt
  ||||||    ;-- vector.SPM_RDY:
  ========< 0x00000064      jmp   sym.__bad_interrupt
  ||||||    0x00000068      sbci  r16, 0xa8
  ||||||    0x0000006a      cpi   r29, 0xb7
  ||||||,=< 0x0000006c      rjmp  0xfffffffffffffce4
  |||||||   0x0000006e      ori   r16, 0xe1
EOF
RUN


NAME=ATTiny48/88
FILE=ihex://bins/avr/attiny48_stepper_driver.hex
CMDS=<<EOF
ia
flt
pd 30 @ 0
EOF
EXPECT=<<EOF
[Info]
arch     avr
cpu      ATTiny88
features N/A
baddr    ----------
binsz    0x00000270
bintype  N/A
bits     8
class    N/A
compiler N/A
dbg_file N/A
endian   LE
hdr.csum N/A
guid     N/A
intrp    N/A
laddr    0x00000000
lang     N/A
machine  ATTiny48/88
maxopsz  4
minopsz  2
os       avr usermode
cc       N/A
pcalign  2
rpath    N/A
subsys   
stripped false
havecode true
va       false
static   true
linenum  false
lsyms    false
canary   false
pie      false
relrocs  false
nx       false

[Imports]
nth vaddr bind type lib name 
-----------------------------

[Entries]
     vaddr      paddr     hvaddr      haddr type    
----------------------------------------------------
0x00000000 0x00000000 ---------- ---------- program
0x00000028 0x00000028 0x00000028 0x00000028 init

[Exports]
nth paddr vaddr bind type size lib name 
----------------------------------------

[Classes]
address min max name super 
---------------------------

[Symbols]
nth      paddr      vaddr bind type size lib name              
---------------------------------------------------------------
  0 0x0000005e 0x0000005e NONE NONE    0     __bad_interrupt
  0 0x00000000 0x00000000 NONE NONE    0     vector.RESET
  0 0x00000028 0x00000028 NONE NONE    0     handler.RESET
  0 0x00000002 0x00000002 NONE NONE    0     vector.EXT_INT0
  0 0x00000004 0x00000004 NONE NONE    0     vector.EXT_INT1
  0 0x00000006 0x00000006 NONE NONE    0     vector.PCINT0
  0 0x00000008 0x00000008 NONE NONE    0     vector.PCINT1
  0 0x0000000a 0x0000000a NONE NONE    0     vector.PCINT2
  0 0x00000060 0x00000060 NONE NONE    0     handler.PCINT2
  0 0x0000000c 0x0000000c NONE NONE    0     vector.PCINT3
  0 0x0000000e 0x0000000e NONE NONE    0     vector.WDT
  0 0x00000010 0x00000010 NONE NONE    0     vector.TIM1_CAPT
  0 0x00000012 0x00000012 NONE NONE    0     vector.TIM1_COMPA
  0 0x00000014 0x00000014 NONE NONE    0     vector.TIM1_COMPB
  0 0x00000016 0x00000016 NONE NONE    0     vector.TIM1_OVF
  0 0x00000018 0x00000018 NONE NONE    0     vector.TIM0_COMPA
  0 0x0000001a 0x0000001a NONE NONE    0     vector.TIM0_COMPB
  0 0x0000001c 0x0000001c NONE NONE    0     vector.TIM0_OVF
  0 0x0000001e 0x0000001e NONE NONE    0     vector.SPI_STC
  0 0x00000020 0x00000020 NONE NONE    0     vector.ADC
  0 0x00000022 0x00000022 NONE NONE    0     vector.EE_RDY
  0 0x00000024 0x00000024 NONE NONE    0     vector.ANA_COMP
  0 0x00000026 0x00000026 NONE NONE    0     vector.TWI

[Sections]
paddr size vaddr vsize align perm name type flags 
--------------------------------------------------

[Memory]
name size address flags mirror 
-------------------------------

[Strings]
paddr vaddr len size section type string 
-----------------------------------------

      addr size space   name                  realname          
----------------------------------------------------------------
0x00000000    1 symbols entry0                entry0
0x00000000    0 symbols sym.vector.RESET      vector.RESET
0x00000002    0 symbols sym.vector.EXT_INT0   vector.EXT_INT0
0x00000004    0 symbols sym.vector.EXT_INT1   vector.EXT_INT1
0x00000006    0 symbols sym.vector.PCINT0     vector.PCINT0
0x00000008    0 symbols sym.vector.PCINT1     vector.PCINT1
0x0000000a    0 symbols sym.vector.PCINT2     vector.PCINT2
0x0000000c    0 symbols sym.vector.PCINT3     vector.PCINT3
0x0000000e    0 symbols sym.vector.WDT        vector.WDT
0x00000010    0 symbols sym.vector.TIM1_CAPT  vector.TIM1_CAPT
0x00000012    0 symbols sym.vector.TIM1_COMPA vector.TIM1_COMPA
0x00000014    0 symbols sym.vector.TIM1_COMPB vector.TIM1_COMPB
0x00000016    0 symbols sym.vector.TIM1_OVF   vector.TIM1_OVF
0x00000018    0 symbols sym.vector.TIM0_COMPA vector.TIM0_COMPA
0x0000001a    0 symbols sym.vector.TIM0_COMPB vector.TIM0_COMPB
0x0000001c    0 symbols sym.vector.TIM0_OVF   vector.TIM0_OVF
0x0000001e    0 symbols sym.vector.SPI_STC    vector.SPI_STC
0x00000020    0 symbols sym.vector.ADC        vector.ADC
0x00000022    0 symbols sym.vector.EE_RDY     vector.EE_RDY
0x00000024    0 symbols sym.vector.ANA_COMP   vector.ANA_COMP
0x00000026    0 symbols sym.vector.TWI        vector.TWI
0x00000028  256 symbols main                  main
0x00000028    1 symbols entry.init0           entry.init0
0x00000028    0 symbols sym.handler.RESET     handler.RESET
0x0000005e    0 symbols sym.__bad_interrupt   __bad_interrupt
0x00000060    0 symbols sym.handler.PCINT2    handler.PCINT2
            ;-- entry0:
            ;-- vector.RESET:
        ,=< 0x00000000      rjmp  0x28
        |   ;-- vector.EXT_INT0:
       ,==< 0x00000002      rjmp  sym.__bad_interrupt
       ||   ;-- vector.EXT_INT1:
      ,===< 0x00000004      rjmp  sym.__bad_interrupt
      |||   ;-- vector.PCINT0:
     ,====< 0x00000006      rjmp  sym.__bad_interrupt
     ||||   ;-- vector.PCINT1:
    ,=====< 0x00000008      rjmp  sym.__bad_interrupt
    |||||   ;-- vector.PCINT2:
   ,======< 0x0000000a      rjmp  sym.handler.PCINT2
   ||||||   ;-- vector.PCINT3:
  ,=======< 0x0000000c      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.WDT:
  ========< 0x0000000e      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_CAPT:
  ========< 0x00000010      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_COMPA:
  ========< 0x00000012      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_COMPB:
  ========< 0x00000014      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_OVF:
  ========< 0x00000016      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM0_COMPA:
  ========< 0x00000018      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM0_COMPB:
  ========< 0x0000001a      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM0_OVF:
  ========< 0x0000001c      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.SPI_STC:
  ========< 0x0000001e      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.ADC:
  ========< 0x00000020      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.EE_RDY:
  ========< 0x00000022      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.ANA_COMP:
  ========< 0x00000024      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TWI:
  ========< 0x00000026      rjmp  sym.__bad_interrupt
  |||||||   ;-- main:
  |||||||   ;-- entry.init0:
  |||||||   ;-- handler.RESET:
  ||||||`-> 0x00000028      clr   r1
  ||||||    0x0000002a      out   SREG, r1
  ||||||    0x0000002c      ser   r28
  ||||||    0x0000002e      ldi   r29, 0x01
  ||||||    0x00000030      out   SPH, r29
  ||||||    0x00000032      out   SPL, r28
  ||||||    0x00000034      ldi   r17, 0x01
  ||||||    0x00000036      ldi   r26, 0x00
  ||||||    0x00000038      ldi   r27, 0x01
  ||||||    0x0000003a      ldi   r30, 0x60
EOF
RUN

NAME=ATmega16
FILE=ihex://bins/avr/ATmega16_WIFI.hex
CMDS=<<EOF
ia
flt
pd 26 @ 0
EOF
EXPECT=<<EOF
[Info]
arch     avr
cpu      ATmega16
features N/A
baddr    ----------
binsz    0x00001dac
bintype  N/A
bits     8
class    N/A
compiler N/A
dbg_file N/A
endian   LE
hdr.csum N/A
guid     N/A
intrp    N/A
laddr    0x00000000
lang     N/A
machine  ATmega16
maxopsz  4
minopsz  2
os       avr usermode
cc       N/A
pcalign  2
rpath    N/A
subsys   
stripped false
havecode true
va       false
static   true
linenum  false
lsyms    false
canary   false
pie      false
relrocs  false
nx       false

[Imports]
nth vaddr bind type lib name 
-----------------------------

[Entries]
     vaddr      paddr     hvaddr      haddr type    
----------------------------------------------------
0x00000000 0x00000000 ---------- ---------- program
0x00000060 0x00000060 0x00000060 0x00000060 init

[Exports]
nth paddr vaddr bind type size lib name 
----------------------------------------

[Classes]
address min max name super 
---------------------------

[Symbols]
nth      paddr      vaddr bind type size lib name              
---------------------------------------------------------------
  0 0x0000009a 0x0000009a NONE NONE    0     __bad_interrupt
  0 0x00000000 0x00000000 NONE NONE    0     vector.RESET
  0 0x00000060 0x00000060 NONE NONE    0     handler.RESET
  0 0x00000004 0x00000004 NONE NONE    0     vector.EXT_INT0
  0 0x00000008 0x00000008 NONE NONE    0     vector.EXT_INT1
  0 0x0000000c 0x0000000c NONE NONE    0     vector.TIM2_COMP
  0 0x00000010 0x00000010 NONE NONE    0     vector.TIM2_OVF
  0 0x00000014 0x00000014 NONE NONE    0     vector.TIM1_CAPT
  0 0x00000018 0x00000018 NONE NONE    0     vector.TIM1_COMPA
  0 0x0000001c 0x0000001c NONE NONE    0     vector.TIM1_COMPB
  0 0x00000020 0x00000020 NONE NONE    0     vector.TIM1_OVF
  0 0x000007cc 0x000007cc NONE NONE    0     handler.TIM1_OVF
  0 0x00000024 0x00000024 NONE NONE    0     vector.TIM0_OVF
  0 0x00000028 0x00000028 NONE NONE    0     vector.SPI_STC
  0 0x0000002c 0x0000002c NONE NONE    0     vector.USART_RXC
  0 0x0000075e 0x0000075e NONE NONE    0     handler.USART_RXC
  0 0x00000030 0x00000030 NONE NONE    0     vector.USART_UDRE
  0 0x00000034 0x00000034 NONE NONE    0     vector.USART_TXC
  0 0x00000038 0x00000038 NONE NONE    0     vector.ADC
  0 0x0000003c 0x0000003c NONE NONE    0     vector.EE_RDY
  0 0x00000040 0x00000040 NONE NONE    0     vector.ANA_COMP
  0 0x00000044 0x00000044 NONE NONE    0     vector.TWSI
  0 0x00000048 0x00000048 NONE NONE    0     vector.EXT_INT2
  0 0x0000004c 0x0000004c NONE NONE    0     vector.TIM0_COMP
  0 0x00000050 0x00000050 NONE NONE    0     vector.SPM_RDY

[Sections]
paddr size vaddr vsize align perm name type flags 
--------------------------------------------------

[Memory]
name size address flags mirror 
-------------------------------

[Strings]
paddr vaddr len size section type string 
-----------------------------------------

      addr size space   name                  realname          
----------------------------------------------------------------
0x00000000    1 symbols entry0                entry0
0x00000000    0 symbols sym.vector.RESET      vector.RESET
0x00000004    0 symbols sym.vector.EXT_INT0   vector.EXT_INT0
0x00000008    0 symbols sym.vector.EXT_INT1   vector.EXT_INT1
0x0000000c    0 symbols sym.vector.TIM2_COMP  vector.TIM2_COMP
0x00000010    0 symbols sym.vector.TIM2_OVF   vector.TIM2_OVF
0x00000014    0 symbols sym.vector.TIM1_CAPT  vector.TIM1_CAPT
0x00000018    0 symbols sym.vector.TIM1_COMPA vector.TIM1_COMPA
0x0000001c    0 symbols sym.vector.TIM1_COMPB vector.TIM1_COMPB
0x00000020    0 symbols sym.vector.TIM1_OVF   vector.TIM1_OVF
0x00000024    0 symbols sym.vector.TIM0_OVF   vector.TIM0_OVF
0x00000028    0 symbols sym.vector.SPI_STC    vector.SPI_STC
0x0000002c    0 symbols sym.vector.USART_RXC  vector.USART_RXC
0x00000030    0 symbols sym.vector.USART_UDRE vector.USART_UDRE
0x00000034    0 symbols sym.vector.USART_TXC  vector.USART_TXC
0x00000038    0 symbols sym.vector.ADC        vector.ADC
0x0000003c    0 symbols sym.vector.EE_RDY     vector.EE_RDY
0x00000040    0 symbols sym.vector.ANA_COMP   vector.ANA_COMP
0x00000044    0 symbols sym.vector.TWSI       vector.TWSI
0x00000048    0 symbols sym.vector.EXT_INT2   vector.EXT_INT2
0x0000004c    0 symbols sym.vector.TIM0_COMP  vector.TIM0_COMP
0x00000050    0 symbols sym.vector.SPM_RDY    vector.SPM_RDY
0x00000060  256 symbols main                  main
0x00000060    1 symbols entry.init0           entry.init0
0x00000060    0 symbols sym.handler.RESET     handler.RESET
0x0000009a    0 symbols sym.__bad_interrupt   __bad_interrupt
0x0000075e    0 symbols sym.handler.USART_RXC handler.USART_RXC
0x000007cc    0 symbols sym.handler.TIM1_OVF  handler.TIM1_OVF
            ;-- entry0:
            ;-- vector.RESET:
        ,=< 0x00000000      jmp   0x60
        |   ;-- vector.EXT_INT0:
       ,==< 0x00000004      jmp   sym.__bad_interrupt
       ||   ;-- vector.EXT_INT1:
      ,===< 0x00000008      jmp   sym.__bad_interrupt
      |||   ;-- vector.TIM2_COMP:
     ,====< 0x0000000c      jmp   sym.__bad_interrupt
     ||||   ;-- vector.TIM2_OVF:
    ,=====< 0x00000010      jmp   sym.__bad_interrupt
    |||||   ;-- vector.TIM1_CAPT:
   ,======< 0x00000014      jmp   sym.__bad_interrupt
   ||||||   ;-- vector.TIM1_COMPA:
  ,=======< 0x00000018      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_COMPB:
  ========< 0x0000001c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_OVF:
  ========< 0x00000020      jmp   sym.handler.TIM1_OVF
  |||||||   ;-- vector.TIM0_OVF:
  ========< 0x00000024      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.SPI_STC:
  ========< 0x00000028      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART_RXC:
  ========< 0x0000002c      jmp   sym.handler.USART_RXC
  |||||||   ;-- vector.USART_UDRE:
  ========< 0x00000030      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.USART_TXC:
  ========< 0x00000034      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.ADC:
  ========< 0x00000038      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.EE_RDY:
  ========< 0x0000003c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.ANA_COMP:
  ========< 0x00000040      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TWSI:
  ========< 0x00000044      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.EXT_INT2:
  ========< 0x00000048      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.TIM0_COMP:
  ========< 0x0000004c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.SPM_RDY:
  ========< 0x00000050      jmp   sym.__bad_interrupt
  |||||||   0x00000054      ori   r22, 0x43
  |||||||   0x00000056      ori   r22, 0xe9
  |||||||   0x00000058      andi  r22, 0x0f
  |||||||   0x0000005a      andi  r23, 0x53
  |||||||   0x0000005c      subi  r23, 0x88
EOF
RUN

NAME=ATmega8/L
FILE=ihex://bins/avr/usbasp.atmega8.2009-02-28.hex
CMDS=<<EOF
ia
flt
pd 26 @ 0
EOF
EXPECT=<<EOF
[Info]
arch     avr
cpu      ATmega8
features N/A
baddr    ----------
binsz    0x00000ef2
bintype  N/A
bits     8
class    N/A
compiler N/A
dbg_file N/A
endian   LE
hdr.csum N/A
guid     N/A
intrp    N/A
laddr    0x00000000
lang     N/A
machine  ATmega8/L
maxopsz  4
minopsz  2
os       avr usermode
cc       N/A
pcalign  2
rpath    N/A
subsys   
stripped false
havecode true
va       false
static   true
linenum  false
lsyms    false
canary   false
pie      false
relrocs  false
nx       false

[Imports]
nth vaddr bind type lib name 
-----------------------------

[Entries]
     vaddr      paddr     hvaddr      haddr type    
----------------------------------------------------
0x00000000 0x00000000 ---------- ---------- program
0x00000078 0x00000078 0x00000078 0x00000078 init

[Exports]
nth paddr vaddr bind type size lib name 
----------------------------------------

[Classes]
address min max name super 
---------------------------

[Symbols]
nth      paddr      vaddr bind type size lib name              
---------------------------------------------------------------
  0 0x000000ae 0x000000ae NONE NONE    0     __bad_interrupt
  0 0x00000000 0x00000000 NONE NONE    0     vector.RESET
  0 0x00000078 0x00000078 NONE NONE    0     handler.RESET
  0 0x00000002 0x00000002 NONE NONE    0     vector.EXT_INT0
  0 0x00000350 0x00000350 NONE NONE    0     handler.EXT_INT0
  0 0x00000004 0x00000004 NONE NONE    0     vector.EXT_INT1
  0 0x00000006 0x00000006 NONE NONE    0     vector.TIM2_COMP
  0 0x00000008 0x00000008 NONE NONE    0     vector.TIM2_OVF
  0 0x0000000a 0x0000000a NONE NONE    0     vector.TIM1_CAPT
  0 0x0000000c 0x0000000c NONE NONE    0     vector.TIM1_COMPA
  0 0x0000000e 0x0000000e NONE NONE    0     vector.TIM1_COMPB
  0 0x00000010 0x00000010 NONE NONE    0     vector.TIM1_OVF
  0 0x00000012 0x00000012 NONE NONE    0     vector.TIM0_OVF
  0 0x00000014 0x00000014 NONE NONE    0     vector.SPI_STC
  0 0x00000016 0x00000016 NONE NONE    0     vector.USART_RXC
  0 0x00000018 0x00000018 NONE NONE    0     vector.USART_UDRE
  0 0x0000001a 0x0000001a NONE NONE    0     vector.USART_TXC
  0 0x0000001c 0x0000001c NONE NONE    0     vector.ADC
  0 0x0000001e 0x0000001e NONE NONE    0     vector.EE_RDY
  0 0x00000020 0x00000020 NONE NONE    0     vector.ANA_COMP
  0 0x00000022 0x00000022 NONE NONE    0     vector.TWSI
  0 0x00000024 0x00000024 NONE NONE    0     vector.SPM_RDY

[Sections]
paddr size vaddr vsize align perm name type flags 
--------------------------------------------------

[Memory]
name size address flags mirror 
-------------------------------

[Strings]
paddr vaddr len size section type string 
-----------------------------------------

      addr size space   name                  realname          
----------------------------------------------------------------
0x00000000    1 symbols entry0                entry0
0x00000000    0 symbols sym.vector.RESET      vector.RESET
0x00000002    0 symbols sym.vector.EXT_INT0   vector.EXT_INT0
0x00000004    0 symbols sym.vector.EXT_INT1   vector.EXT_INT1
0x00000006    0 symbols sym.vector.TIM2_COMP  vector.TIM2_COMP
0x00000008    0 symbols sym.vector.TIM2_OVF   vector.TIM2_OVF
0x0000000a    0 symbols sym.vector.TIM1_CAPT  vector.TIM1_CAPT
0x0000000c    0 symbols sym.vector.TIM1_COMPA vector.TIM1_COMPA
0x0000000e    0 symbols sym.vector.TIM1_COMPB vector.TIM1_COMPB
0x00000010    0 symbols sym.vector.TIM1_OVF   vector.TIM1_OVF
0x00000012    0 symbols sym.vector.TIM0_OVF   vector.TIM0_OVF
0x00000014    0 symbols sym.vector.SPI_STC    vector.SPI_STC
0x00000016    0 symbols sym.vector.USART_RXC  vector.USART_RXC
0x00000018    0 symbols sym.vector.USART_UDRE vector.USART_UDRE
0x0000001a    0 symbols sym.vector.USART_TXC  vector.USART_TXC
0x0000001c    0 symbols sym.vector.ADC        vector.ADC
0x0000001e    0 symbols sym.vector.EE_RDY     vector.EE_RDY
0x00000020    0 symbols sym.vector.ANA_COMP   vector.ANA_COMP
0x00000022    0 symbols sym.vector.TWSI       vector.TWSI
0x00000024    0 symbols sym.vector.SPM_RDY    vector.SPM_RDY
0x00000078  256 symbols main                  main
0x00000078    1 symbols entry.init0           entry.init0
0x00000078    0 symbols sym.handler.RESET     handler.RESET
0x000000ae    0 symbols sym.__bad_interrupt   __bad_interrupt
0x00000350    0 symbols sym.handler.EXT_INT0  handler.EXT_INT0
            ;-- entry0:
            ;-- vector.RESET:
        ,=< 0x00000000      rjmp  0x78
        |   ;-- vector.EXT_INT0:
       ,==< 0x00000002      rjmp  sym.handler.EXT_INT0
       ||   ;-- vector.EXT_INT1:
      ,===< 0x00000004      rjmp  sym.__bad_interrupt
      |||   ;-- vector.TIM2_COMP:
     ,====< 0x00000006      rjmp  sym.__bad_interrupt
     ||||   ;-- vector.TIM2_OVF:
    ,=====< 0x00000008      rjmp  sym.__bad_interrupt
    |||||   ;-- vector.TIM1_CAPT:
   ,======< 0x0000000a      rjmp  sym.__bad_interrupt
   ||||||   ;-- vector.TIM1_COMPA:
  ,=======< 0x0000000c      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_COMPB:
  ========< 0x0000000e      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM1_OVF:
  ========< 0x00000010      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TIM0_OVF:
  ========< 0x00000012      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.SPI_STC:
  ========< 0x00000014      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.USART_RXC:
  ========< 0x00000016      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.USART_UDRE:
  ========< 0x00000018      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.USART_TXC:
  ========< 0x0000001a      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.ADC:
  ========< 0x0000001c      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.EE_RDY:
  ========< 0x0000001e      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.ANA_COMP:
  ========< 0x00000020      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.TWSI:
  ========< 0x00000022      rjmp  sym.__bad_interrupt
  |||||||   ;-- vector.SPM_RDY:
  ========< 0x00000024      rjmp  sym.__bad_interrupt
  |||||||   0x00000026      mulsu r16, r20
  |||||||   0x00000028      cpc   r0, r9
  |||||||   0x0000002a      fmul  r17, r20
  |||||||   0x0000002c      invalid
  |||||||   0x0000002e      invalid
  |||||||   0x00000030      invalid
  |||||||   0x00000032      invalid
EOF
RUN

NAME=ATmel Unknown
FILE=bins/firmware/arduino_avr.bin
CMDS=<<EOF
ia
flt
pd 60 @ 0
EOF
EXPECT=<<EOF
[Info]
arch     avr
cpu      ATmega8
features N/A
baddr    ----------
binsz    0x00003722
bintype  N/A
bits     8
class    N/A
compiler N/A
dbg_file N/A
endian   LE
hdr.csum N/A
guid     N/A
intrp    N/A
laddr    0x00000000
lang     N/A
machine  ATmel (unknown)
maxopsz  4
minopsz  2
os       avr usermode
cc       N/A
pcalign  2
rpath    N/A
subsys   
stripped false
havecode true
va       false
static   true
linenum  false
lsyms    false
canary   false
pie      false
relrocs  false
nx       false

[Imports]
nth vaddr bind type lib name 
-----------------------------

[Entries]
     vaddr      paddr     hvaddr      haddr type    
----------------------------------------------------
0x00000000 0x00000000 ---------- ---------- program
0x00000158 0x00000158 0x00000158 0x00000158 init

[Exports]
nth paddr vaddr bind type size lib name 
----------------------------------------

[Classes]
address min max name super 
---------------------------

[Symbols]
nth      paddr      vaddr bind type size lib name               
----------------------------------------------------------------
  0 0x000001b6 0x000001b6 NONE NONE    0     __bad_interrupt
  0 0x00000000 0x00000000 NONE NONE    0     vector.RESET
  0 0x00000158 0x00000158 NONE NONE    0     handler.RESET
  0 0x00000004 0x00000004 NONE NONE    0     vector.unknown_2
  0 0x00000008 0x00000008 NONE NONE    0     vector.unknown_4
  0 0x0000000c 0x0000000c NONE NONE    0     vector.unknown_6
  0 0x00000010 0x00000010 NONE NONE    0     vector.unknown_8
  0 0x00000014 0x00000014 NONE NONE    0     vector.unknown_a
  0 0x00000018 0x00000018 NONE NONE    0     vector.unknown_c
  0 0x0000001c 0x0000001c NONE NONE    0     vector.unknown_e
  0 0x00000020 0x00000020 NONE NONE    0     vector.unknown_10
  0 0x00000024 0x00000024 NONE NONE    0     vector.unknown_12
  0 0x00000028 0x00000028 NONE NONE    0     vector.unknown_14
  0 0x0000002c 0x0000002c NONE NONE    0     vector.unknown_16
  0 0x00000030 0x00000030 NONE NONE    0     vector.unknown_18
  0 0x00000034 0x00000034 NONE NONE    0     vector.unknown_1a
  0 0x00000038 0x00000038 NONE NONE    0     vector.unknown_1c
  0 0x0000003c 0x0000003c NONE NONE    0     vector.unknown_1e
  0 0x00000040 0x00000040 NONE NONE    0     vector.unknown_20
  0 0x000003f8 0x000003f8 NONE NONE    0     handler.unknown_20
  0 0x00000044 0x00000044 NONE NONE    0     vector.unknown_22
  0 0x00000048 0x00000048 NONE NONE    0     vector.unknown_24
  0 0x0000143a 0x0000143a NONE NONE    0     handler.unknown_24
  0 0x0000004c 0x0000004c NONE NONE    0     vector.unknown_26
  0 0x0000154e 0x0000154e NONE NONE    0     handler.unknown_26
  0 0x00000050 0x00000050 NONE NONE    0     vector.unknown_28
  0 0x00000054 0x00000054 NONE NONE    0     vector.unknown_2a
  0 0x00000058 0x00000058 NONE NONE    0     vector.unknown_2c
  0 0x0000005c 0x0000005c NONE NONE    0     vector.unknown_2e
  0 0x00000060 0x00000060 NONE NONE    0     vector.unknown_30
  0 0x00000064 0x00000064 NONE NONE    0     vector.unknown_32
  0 0x00000068 0x00000068 NONE NONE    0     vector.unknown_34
  0 0x0000006c 0x0000006c NONE NONE    0     vector.unknown_36
  0 0x00000070 0x00000070 NONE NONE    0     vector.unknown_38
  0 0x00000074 0x00000074 NONE NONE    0     vector.unknown_3a
  0 0x00000078 0x00000078 NONE NONE    0     vector.unknown_3c
  0 0x000014b0 0x000014b0 NONE NONE    0     handler.unknown_3c
  0 0x0000007c 0x0000007c NONE NONE    0     vector.unknown_3e
  0 0x000015c2 0x000015c2 NONE NONE    0     handler.unknown_3e
  0 0x00000080 0x00000080 NONE NONE    0     vector.unknown_40
  0 0x00000084 0x00000084 NONE NONE    0     vector.unknown_42
  0 0x00000088 0x00000088 NONE NONE    0     vector.unknown_44

[Sections]
paddr size vaddr vsize align perm name type flags 
--------------------------------------------------

[Memory]
name size address flags mirror 
-------------------------------

[Strings]
paddr vaddr len size section type string 
-----------------------------------------

      addr size space   name                   realname           
------------------------------------------------------------------
0x00000000    1 symbols entry0                 entry0
0x00000000    0 symbols sym.vector.RESET       vector.RESET
0x00000004    0 symbols sym.vector.unknown_2   vector.unknown_2
0x00000008    0 symbols sym.vector.unknown_4   vector.unknown_4
0x0000000c    0 symbols sym.vector.unknown_6   vector.unknown_6
0x00000010    0 symbols sym.vector.unknown_8   vector.unknown_8
0x00000014    0 symbols sym.vector.unknown_a   vector.unknown_a
0x00000018    0 symbols sym.vector.unknown_c   vector.unknown_c
0x0000001c    0 symbols sym.vector.unknown_e   vector.unknown_e
0x00000020    0 symbols sym.vector.unknown_10  vector.unknown_10
0x00000024    0 symbols sym.vector.unknown_12  vector.unknown_12
0x00000028    0 symbols sym.vector.unknown_14  vector.unknown_14
0x0000002c    0 symbols sym.vector.unknown_16  vector.unknown_16
0x00000030    0 symbols sym.vector.unknown_18  vector.unknown_18
0x00000034    0 symbols sym.vector.unknown_1a  vector.unknown_1a
0x00000038    0 symbols sym.vector.unknown_1c  vector.unknown_1c
0x0000003c    0 symbols sym.vector.unknown_1e  vector.unknown_1e
0x00000040    0 symbols sym.vector.unknown_20  vector.unknown_20
0x00000044    0 symbols sym.vector.unknown_22  vector.unknown_22
0x00000048    0 symbols sym.vector.unknown_24  vector.unknown_24
0x0000004c    0 symbols sym.vector.unknown_26  vector.unknown_26
0x00000050    0 symbols sym.vector.unknown_28  vector.unknown_28
0x00000054    0 symbols sym.vector.unknown_2a  vector.unknown_2a
0x00000058    0 symbols sym.vector.unknown_2c  vector.unknown_2c
0x0000005c    0 symbols sym.vector.unknown_2e  vector.unknown_2e
0x00000060    0 symbols sym.vector.unknown_30  vector.unknown_30
0x00000064    0 symbols sym.vector.unknown_32  vector.unknown_32
0x00000068    0 symbols sym.vector.unknown_34  vector.unknown_34
0x0000006c    0 symbols sym.vector.unknown_36  vector.unknown_36
0x00000070    0 symbols sym.vector.unknown_38  vector.unknown_38
0x00000074    0 symbols sym.vector.unknown_3a  vector.unknown_3a
0x00000078    0 symbols sym.vector.unknown_3c  vector.unknown_3c
0x0000007c    0 symbols sym.vector.unknown_3e  vector.unknown_3e
0x00000080    0 symbols sym.vector.unknown_40  vector.unknown_40
0x00000084    0 symbols sym.vector.unknown_42  vector.unknown_42
0x00000088    0 symbols sym.vector.unknown_44  vector.unknown_44
0x00000158  256 symbols main                   main
0x00000158    1 symbols entry.init0            entry.init0
0x00000158    0 symbols sym.handler.RESET      handler.RESET
0x000001b6    0 symbols sym.__bad_interrupt    __bad_interrupt
0x000003f8    0 symbols sym.handler.unknown_20 handler.unknown_20
0x0000143a    0 symbols sym.handler.unknown_24 handler.unknown_24
0x000014b0    0 symbols sym.handler.unknown_3c handler.unknown_3c
0x0000154e    0 symbols sym.handler.unknown_26 handler.unknown_26
0x000015c2    0 symbols sym.handler.unknown_3e handler.unknown_3e
            ;-- entry0:
            ;-- vector.RESET:
        ,=< 0x00000000      jmp   main
        |   ;-- vector.unknown_2:
       ,==< 0x00000004      jmp   sym.__bad_interrupt
       ||   ;-- vector.unknown_4:
      ,===< 0x00000008      jmp   sym.__bad_interrupt
      |||   ;-- vector.unknown_6:
     ,====< 0x0000000c      jmp   sym.__bad_interrupt
     ||||   ;-- vector.unknown_8:
    ,=====< 0x00000010      jmp   sym.__bad_interrupt
    |||||   ;-- vector.unknown_a:
   ,======< 0x00000014      jmp   sym.__bad_interrupt
   ||||||   ;-- vector.unknown_c:
  ,=======< 0x00000018      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_e:
  ========< 0x0000001c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_10:
  ========< 0x00000020      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_12:
  ========< 0x00000024      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_14:
  ========< 0x00000028      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_16:
  ========< 0x0000002c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_18:
  ========< 0x00000030      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_1a:
  ========< 0x00000034      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_1c:
  ========< 0x00000038      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_1e:
  ========< 0x0000003c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_20:
  ========< 0x00000040      jmp   sym.handler.unknown_20
  |||||||   ;-- vector.unknown_22:
  ========< 0x00000044      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_24:
  ========< 0x00000048      jmp   sym.handler.unknown_24
  |||||||   ;-- vector.unknown_26:
  ========< 0x0000004c      jmp   sym.handler.unknown_26
  |||||||   ;-- vector.unknown_28:
  ========< 0x00000050      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_2a:
  ========< 0x00000054      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_2c:
  ========< 0x00000058      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_2e:
  ========< 0x0000005c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_30:
  ========< 0x00000060      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_32:
  ========< 0x00000064      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_34:
  ========< 0x00000068      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_36:
  ========< 0x0000006c      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_38:
  ========< 0x00000070      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_3a:
  ========< 0x00000074      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_3c:
  ========< 0x00000078      jmp   sym.handler.unknown_3c
  |||||||   ;-- vector.unknown_3e:
  ========< 0x0000007c      jmp   sym.handler.unknown_3e
  |||||||   ;-- vector.unknown_40:
  ========< 0x00000080      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_42:
  ========< 0x00000084      jmp   sym.__bad_interrupt
  |||||||   ;-- vector.unknown_44:
  ========< 0x00000088      jmp   sym.__bad_interrupt
  |||||||   0x0000008c      nop
  |||||||   0x0000008e      sbc   r0, r0
  |||||||   0x00000090      sbc   r0, r25
  |||||||   0x00000092      nop
  |||||||   0x00000094      nop
  |||||||   0x00000096      nop
  |||||||   0x00000098      mulsu r16, r17
  |||||||   0x0000009a      cpc   r16, r4
  |||||||   0x0000009c      nop
  |||||||   0x0000009e      nop
  |||||||   0x000000a0      nop
  |||||||   0x000000a2      nop
  |||||||   0x000000a4      nop
  |||||||   0x000000a6      nop
  |||||||   0x000000a8      nop
  |||||||   0x000000aa      nop
  |||||||   0x000000ac      nop
  |||||||   0x000000ae      nop
  |||||||   0x000000b0      nop
  |||||||   0x000000b2      nop
  |||||||   0x000000b4      nop
  |||||||   0x000000b6      nop
  |||||||   0x000000b8      nop
  |||||||   0x000000ba      nop
  |||||||   0x000000bc      nop
EOF
RUN

NAME=ATmega328p iH
FILE=ihex://bins/avr/grbl_0_51_atmega328p_16mhz_9600.hex
CMDS=iH
EXPECT=<<EOF
avr:
  board: "ATmega328p"
  cpu: "ATmega328p"
  reset_vector:
    address: 0x0
    handler: 0x280
  interrupt_vector_size: 4
  num_interrupts: 26
  bad_interrupt: 0x2ba

EOF
RUN